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參數資料
型號: TMC2360KLC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 顏色信號轉換
英文描述: COLOR SIGNAL ENCODER, PQFP80
封裝: 2.70 MM HEIGHT, MQFP-80
文件頁數: 12/24頁
文件大小: 158K
代理商: TMC2360KLC
TMC2360
PRODUCT SPECIFICATION
2
Functional Description
The TMC2360 is a VGA to Video converter capable of pro-
ducing video signals conforming to NTSC and PAL stan-
dards using a single low-cost application circuit. Within the
TMC2360 is all of the active circuitry required to generate a
television signal with outstanding image quality in a stand-
alone application.
Incoming VGA source signals must be 2X the frame and 2X
the line rate of the outgoing TV standard within a
±2% toler-
ance. Supported VGA formats are 640x480 at 60 Hz for
NTSC and PAL-M, and 640x480 and 800x600 at 50 Hz for
PAL B/G/H/I.
The TMC2360 is ideal for portable converter applications, as
well as integration into notebook and palmtop computers and
video games.
Input Section
Analog VGA signals are digitized by three 8-bit A/D con-
verters, operating at rates of up to 36 Ms/s. The signal range
is 0 to 700 mV established by the reference voltage, VRT.
By connecting VTOUT to VRT, the A/D converter reference
voltage may be supplied by an on-chip voltage follower with
an input, VTIN, that may be varied from 0 to 2 volts to
accommodate different input levels.
Clock Processor
Two phase-locked loops synthesize clocks from the VGA
Horizontal Sync signal. One loop generates ADCLK, which
is used internally as the A/D sample clock. A second PLL
generates PXCK, which is used internally as the digital
encoder clock.
Either internal or external phase-locked loops may be
selected by programming pins A1 and A0. For internal loops,
loop lters must be connected to LPFA and LPFP.
With external phase-locked loops, the internal divide by N
and divide by M counters are still used. Only the phase
detector, charge pump and VCO need be located in the exter-
nal controller.
A stable timebase reference for subcarrier generation is
derived from a 27 MHz crystal, or a TTL clock applied to pin
XTAL1.
To synchronize the video encoder, vertical timing is derived
from VGAVS, the VGA vertical sync signal. VGAHS and
VGAVS signals of either polarity are accepted.
VESA Display Power Management Signaling functions may
be enabled with the DPMS pin. Using the DPMS protocol,
operational commands may be communicated to the
TMC2360 via VGAHS and VGAVS signals. DPMS
STAND-BY or DPMS SUSPEND modes set the processor
to sleep and blanks the screen. DPMS OFF sets the proces-
sor, A/Ds and D/As to sleep with a blanked screen.
Vertical Sync Communications may be enabled with the
VSCOM pin to detect the number of VGAHS pulses during
the VGAVS period. With VSCOM, the Flicker Filter mode
and the Video Standard may be selected by commands com-
municated via the VGA sync signals.
Flicker Filter
Flicker may be traded-off against vertical resolution with a
three-line adaptive icker lter. A single toggle pin (FIL)
selects either High Filter, Medium Filter, or No Filter modes.
A fourth mode, Color Bars, is useful for video setup and as a
reference point for lter selection.
Video Encoder
Unless VSCOM is enabled, TVSTD1-0 pins select the TV
standard to be either NTSC, PAL or PAL-M.
Relative to the bezel framed by horizontal and vertical sync,
the image may be moved right/left, and down/up by pulsing
the POSR and POSD pins. BLANK suppreses the image, set-
ting the screen either black or blue according to the state of
the BLUE pin.
NTSC (SMPTE 170M) and PAL (CCIR 624) video signals
are produced by three 9-bit D/A converters that can drive the
37.5
load of a double-terminated 75 line. Digital 2X
oversampling minimizes sinX/X distortion, facilitating use
of low-cost output lters.
Composite and S-Video D/As are independently enabled via
CVIDEN and SVIDEN pins to minimize power dissipation.
Control Processor
TMC2360 setup and control is derived from external
switches and push buttons. Schmitt trigger inputs reject
external noise. Unused controls may be preset by hardwiring
inputs to ground or VCC.
Encoder Output Current
Output current is established by VREF and an external resis-
tor connected between RREF and ground. An internal 1.235
volt reference is buffered from VREF by a resistor, so VREF
may be overridden by an external voltage. Output current
may be calibrated by resistor selection or setting a potenti-
ometer attached to RREF.
To minimize DAC noise, a bypass capacitor must be con-
nected from CBYPR to an adjacent VDDA pin.
Microprocessor Port
Instead of utilizing control pin inputs, two operational
modes, TV Standard and Flicker Filter, may be selected by
writing to the VGA control register. Five registers may be
read: address, VGA0, VGA1, Revision ID and Part ID.
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