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參數資料
| 型號： | TMC2360KLC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP80 |
| 封裝： | 2.70 MM HEIGHT, MQFP-80 |
| 文件頁數： | 2/24頁 |
| 文件大小： | 158K |
| 代理商： | TMC2360KLC |
TMC2360
PRODUCT SPECIFICATION
10
Table 9. Display Power Management Signaling (DPMS) States
Table 10. TVSTD Control When Under Software Control (VSCOM = 1)
State
VGAHS
VGAVS
TMC2360 State
On
Pulses
On, video active
Stand-by
No Pulses
Pulses
Stand-by, screen blanked (color set by BLUE)
Suspend
Pulses
No Pulses
Stand-by, screen blanked (color set by BLUE)
Off
No Pulses
Off, screen black (equivalent to PWRDN, except A/D Clock
and 27MHZ oscillator are active.)
TVSTD1-0
Hsyncs per Vsync Interval
Television Standard
VGA Frame Rate
XX
10,11,12
PAL 800 (B, G, I)
50 Hz
X0
6,7,9
PAL 640 (B, G, I)
50 Hz
01
6,7,9
PAL-M
60 Hz
11
6,7,9
(reserved)
0X
1-5,8,14,15
NTSC-EIAJ
60 Hz
10
1-5,8,14,15
NTSC
60 Hz
11
1-5,8,14,15
(reserved)
XX
0,13
Blank (with prior standard)
50/60 Hz
Table 11. VSCOM Filter Command
Interpretation (VSCOM=1)
Microprocessor Interface
Table 12 shows the ve registers that may be read after the
Address Register has been loaded. Only the two VGA regis-
ters and the Address Register may be written. For micropro-
cessor control, 40h must be written into VGA register 1. To
disable control through VGA Register 0, 00h must be written
into register 1. Bit assignments of VGA register 0 are listed
in Table 13. Bit assignments of VGA register 1 are listed in
Table 14.
For communications through the microprocessor port, set
MPEN = HIGH. Read and write timing is shown in Figure 3
and Figure 4. To access a VGA register, write the address of
the selected register into the lower four bits of the eight bit
Address Register with A0 = LOW. Then with A0 = HIGH,
read or write to the selected register.
HSYNCs per VSYNC
Interval
Filter Mode
5, 9, 12
No Filter
4, 7, 11
2-line filter
1, 2, 3, 6, 8, 10, 14, 15
3-line filter
0, 13
Blank (with prior mode)
Table 12. Microprocessor Addressable
Registers
Table 13. VGA Control Register 0 Bit Map
A1
A0
Address
Register Value
Register
0
x
Address Register
0
1
x0
VGA Register 0
0
1
x1
VGA Register 1
0
1
x6
Revision ID (xxh)
0
1
x7
Part ID (0Fh)
Bit #
Name
Function
7
—
0 (reserved)
6-5
FIL
0 0 No Filter
0 1 2-line Filter
1 x 3-line Filter
4-2
TVSTD
0 0 0 NTSC-EIA
0 0 1 NTSC
0 1 0 PALM
0 1 1 PAL640
1 x x PAL800
1-0
VIDEO
0 0 Black
0 1 Ramp
1 0 Color Bars
1 1 Normal
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