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參數資料
| 型號： | TMP320C6413ZTSA500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 14/140頁 |
| 文件大小： | 1958K |
| 代理商： | TMP320C6413ZTSA500 |
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Device Characteristics
14
April 2004
Revised May 2005
SPRS247E
The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may
be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows
debugger interface for visibility into
source code execution.
2.3
Device Characteristics
Table 2
1, provides an overview of the C6413 and C6410 DSPs. The tables show significant features of the
C6413 and C6410 devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and
the package type with pin count.
Table 2
1. Characteristics of the C6413 and C6410 Processors
HARDWARE FEATURES
EMIFA (32-bit bus width)
(clock source = AECLKIN, CLKOUT4, or CLKOUT6)
C6413 AND C6410
1
EDMA (64 independent channels)
McASPs (use Peripheral Clock and AUXCLK)
I2Cs (use Peripheral Clock)
HPI (32- or 16-bit user selectable)
McBSPs
(internal clock source = CPU/4 clock frequency)
1
2
2
Peripherals
Not all peripherals pins
are available at the
i
(F
same time (For more
detail, see the Device
Configuration section).
1 (HPI16 or HPI32)
2
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
3
General-Purpose Input/Output Port (GP0)
16
Size (Bytes)
288K (
C6413
)
160K (
C6410
)
On-Chip Memory
Organization
16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
256KB Unified Mapped RAM/Cache (L2) [
C6413
]
128KB Unified Mapped RAM/Cache (L2) [
C6410
]
0x0C01
0x0007902F
500 (
C6413
)
400 (
C6410
)
CPU ID + CPU Rev ID
JTAG BSDL_ID
Control Status Register (CSR.[31:16])
JTAGID register (address location: 0x01B3F008)
Frequency
MHz
Cycle Time
ns
2 ns (
C6413-500, C6413 A
500
)
[500 MHz CPU, 100 MHz EMIF
]
2.5 ns (
C6410-400, C6410 A
400
)
[400 MHz CPU, 100 MHz EMIF
]
1.2 V
3.3 V
Bypass (x1), x5, x6, x7, x8, x9, x10, x11, x12, x16,
x18, x19, x20, x21, x22, and x24
Voltage
Core (V)
I/O (V)
PLL Options
CLKIN frequency multiplier
BGA Package
Process Technology
23 x 23 mm
μ
m
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
288-Pin Flip-Chip Plastic BGA (GTS and ZTS)
0.13
μ
m
Product Status
PD
On this C64x
device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
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