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參數資料
| 型號： | TMP320C6413ZTSA500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 88/140頁 |
| 文件大?。?/td> | 1958K |
| 代理商： | TMP320C6413ZTSA500 |
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Bootmode
88
April 2004
Revised May 2005
SPRS247E
4.12
Bootmode
The C6413/C6410 device resets using the active-low signal RESET. While RESET is low, the device is held
in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed
device configuration and boot mode.
The C6413/C6410 has three types of boot modes:
Host boot
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the C6413/C6410 device, the HPI peripheral is used for host boot
providing the TOUT0/HPI_EN pin is low, enabling the HPI peripheral [default]. Once the host is finished
with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot
process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The
CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it
occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only
if the host boot process is selected. All memory may be written to and read by the host. This allows for the
host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs
to clear the DSPINT, otherwise, no more DSPINTs can be received.
EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
4.13
Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power-up.
Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
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