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參數(shù)資料
型號： TMP320C6413ZTSA500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 97/140頁
文件大?。?/td> 1958K
代理商： TMP320C6413ZTSA500
Asynchronous Memory Timing
97
April 2004
Revised May 2005
SPRS247E
7.2
Asynchronous Memory Timing
Table 7
8. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(see Figure 7
7 and Figure 7
8)
NO.
400
500
UNIT
MIN
6.5
MAX
3
4
6
7
t
su(EDV-AREH)
t
h(AREH-EDV)
t
su(ARDY-EKO1H)
t
h(EKO1H-ARDY)
Setup time, AEDx valid before AARE high
Hold time, AEDx valid after AARE high
Setup time, AARDY valid before AECLKOUTx high
Hold time, AARDY valid after AECLKOUTx high
ns
ns
ns
ns
1
3
3
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. The ARDY signal is
only
recognized two cycles before the end of the programmed strobe time
and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after
ARDY is recognized high To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width
= 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
Table 7
9. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
§
(see Figure 7
7 and Figure 7
8)
NO.
PARAMETER
400
500
UNIT
MIN
MAX
1
2
5
8
9
10
t
osu(SELV-AREL)
t
oh(AREH-SELIV)
t
d(EKO1H-AREV)
t
osu(SELV-AWEL)
t
oh(AWEH-SELIV)
t
d(EKO1H-AWEV)
Output setup time, select signals valid to AARE low
Output hold time, AARE high to select signals invalid
Delay time, AECLKOUTx high to AARE valid
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUTx high to AAWE valid
RS * E
1.5
RH * E
1.9
ns
ns
ns
ns
ns
ns
1
7
WS * E
1.7
WH * E
1.8
1.3
7.1
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
E = ECLKOUT1 period in ns for EMIFA
Select signals for EMIFA include: ACEx, ABE[3.:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].
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