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參數(shù)資料
型號(hào)： TMP320F2810PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 67/103頁(yè)
文件大小： 1341K
代理商： TMP320F2810PBKS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
67
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of
a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
12-bit ADC core with built-in S/H
Analog input: 0 V to 2.5 V
Fast conversion time:
–
Single conversion time: 200 ns
–
Pipelined conversion time: 60 ns
16-channel, muxed inputs
Autosequencing capability provides up to 16
“
autoconversions
”
in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Digital Value
4095
Input Analog Voltage
ADCLO
2.5
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
S/W
–
software immediate start
–
EVA
–
Event manager A (multiple event sources within EVA)
–
EVB
–
Event manager B (multiple event sources within EVB)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in
“
start/stop
”
mode, allowing multiple
“
time-sequenced triggers
”
to synchronize
conversions
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
Calibration mode
P
相關(guān)PDF資料
PDF描述
TMP320F2810GHHA DIGITAL SIGNAL PROCESSORS
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TMP320F2810GHHS DIGITAL SIGNAL PROCESSORS
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