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參數資料
型號： TMP320F2810PBKS
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數字信號處理器
文件頁數： 85/103頁
文件大小： 1341K
代理商： TMP320F2810PBKS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
85
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
GPIO mux
The GPIO Mux registers, are used to select the operation of shared pins on the F2810 and F2812 devices. The
pins can be individually selected to operate as
“
Digital I/O
”
or connected to
“
Peripheral I/O
”
signals (via the
GPxMUX registers). If selected for
“
Digital I/O
”
mode, registers are provided to configure the pin direction (via
the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers).
Table 60 lists the GPIO Mux Registers.
Table 60. GPIO Mux Registers
§
NAME
ADDRESS
SIZE (x16)
REGISTER DESCRIPTION
GPAMUX
0x0000
–
70C0
1
GPIO A Mux Control Register
GPADIR
0x0000
–
70C1
1
GPIO A Direction Control Register
GPAQUAL
0x0000
–
70C2
1
GPIO A Input Qualification Control Register
reserved
0x0000
–
70C3
1
GPBMUX
0x0000
–
70C4
1
GPIO B Mux Control Register
GPBDIR
0x0000
–
70C5
1
GPIO B Direction Control Register
GPBQUAL
0x0000
–
70C6
1
GPIO B Input Qualification Control Register
reserved
0x0000
–
70C7
1
reserved
0x0000
–
70C8
1
reserved
0x0000
–
70C9
1
reserved
0x0000
–
70CA
1
reserved
0x0000
–
70CB
1
GPDMUX
0x0000
–
70CC
1
GPIO D Mux Control Register
GPDDIR
0x0000
–
70CD
1
GPIO D Direction Control Register
GPDQUAL
0x0000
–
70CE
1
GPIO D Input Qualification Control Register
reserved
0x0000
–
70CF
1
GPEMUX
0x0000
–
70D0
1
GPIO E Mux Control Register
GPEDIR
0x0000
–
70D1
1
GPIO E Direction Control Register
GPEQUAL
0x0000
–
70D2
1
GPIO E Input Qualification Control Register
reserved
0x0000
–
70D3
1
GPFMUX
0x0000
–
70D4
1
GPIO F Mux Control Register
GPFDIR
0x0000
–
70D5
1
GPIO F Direction Control Register
reserved
0x0000
–
70D6
1
reserved
0x0000
–
70D7
1
GPGMUX
0x0000
–
70D8
1
GPIO F Mux Control Register
GPGDIR
0x0000
–
70D9
1
GPIO F Direction Control Register
reserved
0x0000
–
70DA
1
reserved
0x0000
–
70DB
1
reserved
0x0000
–
70DC
0x0000
–
70DF
4
Registers that are not implemented will return undefined values and writes will be ignored.
Not all inputs will support input signal qualification.
§
These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
P
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