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參數資料
| 型號： | TPA2026D2YZHR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PBGA16 |
| 封裝： | 2.20 X 2.20 MM, GREEN, DSBGA-16 |
| 文件頁數： | 16/39頁 |
| 文件大小： | 823K |
| 代理商： | TPA2026D2YZHR |
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Register(N)
8-BitDatafor
Register(N+1)
www.ti.com
SLOS649A – MARCH 2010 – REVISED JANUARY 2011
TPA2026D2 AGC RECOMMENDED SETTINGS
Table 2. Recommended AGC Settings for Different Types of Audio Source (VDD = 3.6 V)
AUDIO
COMPRESSION
ATTACK TIME
RELEASE TIME
HOLD TIME
FIXED GAIN
LIMITER LEVEL
SOURCE
RATIO
(ms/6 dB)
(ms)
(dB)
(dBV)
Pop Music
4:1
1.28 to 3.84
986 to 1640
137
6
7.5
Classical
2:1
2.56
1150
137
6
8
Jazz
2:1
5.12 to 10.2
3288
—
6
8
Rap/Hip Hop
4:1
1.28 to 3.84
1640
—
6
7.5
Rock
2:1
3.84
4110
—
6
8
Voice/News
4:1
2.56
1640
—
6
8.5
GENERAL I
2C OPERATION
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most
significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on
SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within
the low time of the clock period. Figure 42 shows a typical sequence. The master generates the 7-bit slave
address and the read/write (R/W) bit to open communication with another device, and then waits for an
acknowledge condition. The TPA2026D2 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 5 V, use pull-up resistors between 1 k
and 2 k.
Figure 42. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 42.
SINGLE-AND MULTIPLE-BYTE TRANSFERS
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA2026D2 responds with data, one byte at a time, starting at the
register assigned, as long as the master device continues to respond with acknowledgments.
The TPA2026D2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of
data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.
Copyright 2010–2011, Texas Instruments Incorporated
23
Product Folder Link(s): TPA2026D2
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