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參數資料
| 型號： | TPA2051D3YFFT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2.9 W, 2 CHANNEL, AUDIO AMPLIFIER, PBGA25 |
| 封裝： | 2.16 X 2.11 MM, 0.40 MM PITCH, GREEN, WCSP-25 |
| 文件頁數： | 7/34頁 |
| 文件大小： | 1594K |
| 代理商： | TPA2051D3YFFT |
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SINGLE-AND MULTIPLE-BYTE TRANSFERS
SINGLE-BYTE WRITE
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0 ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2CDevice Addressand
Read/WriteBit
Register
DataByte
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
Register
SINGLE-BYTE READ
www.ti.com ..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 34.
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA2051D3 responds with data, a byte at a time, starting at the
register assigned, as long as the master device continues to respond with acknowledges.
The TPA2051D3 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken
place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount
of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are
written.
As shown in Figure 35, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TPA2051D3 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TPA2051D3 internal memory address being accessed. After
receiving the register byte, the TPA2051D3 again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data write transfer.
Figure 35. Single-Byte Write Transfer
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA2051D3 as shown in Figure 36. After receiving each data byte,
the TPA2051D3 responds with an acknowledge bit.
Figure 36. Multiple-Byte Write Transfer
As shown in Figure 37, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA2051D3 address and the read/write bit, the TPA2051D3 responds with an acknowledge
Copyright 2009, Texas Instruments Incorporated
15
Product Folder Link(s): TPA2051D3
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