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參數(shù)資料
| 型號： | TPA2051D3YFFT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2.9 W, 2 CHANNEL, AUDIO AMPLIFIER, PBGA25 |
| 封裝： | 2.16 X 2.11 MM, 0.40 MM PITCH, GREEN, WCSP-25 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 1594K |
| 代理商： | TPA2051D3YFFT |
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A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2CDevice Addressand
Read/WriteBit
Register
DataByte
D7
D6
D1
D0 ACK
I2CDevice Addressand
Read/WriteBit
Not
Acknowledge
R/W
A1
RepeatStart
Condition
MULTIPLE-BYTE READ
A6
A0
ACK
Acknowledge
I2CDevice Addressand
Read/WriteBit
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I2CDevice Addressand
Read/WriteBit
Register
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
REGISTER MAPS
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 ..................................................................................................................................................... www.ti.com
bit. The master then sends the internal memory address byte, after which the TPA2051D3 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA2051D3 address and
the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TPA2051D3
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Figure 37. Single-Byte Read Transfer
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA2051D3 to the master device as shown in Figure 38. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 38. Multiple-Byte Read Transfer
REGISTER BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0 Version[3]
Version[2]
Version[1]
Version[0]
Reserved
Spk_Fault
Thermal
1 LIM_SEL
LIM_EN
Reserved
SWS
HPL_Enable
HPR_Enable
Spk_Enable
VM_Bypass
2 ATK_time[4]
ATK_time[3]
ATK_time[2]
ATK_time[1]
ATK_time[0]
LIMSPK[2]
LIMSPK[1]
LIMSPK[0]
3 REL_time[4]
REL_time[3]
REL_time[2]
REL_time[1]
REL_time[0]
LIMHP[2]
LIMHP[1]
LIMHP[0]
4 Mode[2]
Mode[1]
Mode[0]
MON_Vol[4]
MON_Vol[3]
MON_Vol[2]
MON_Vol[1]
MON_Vol[0]
5 SPK_Gain
HP_0dB
Reserved
ST1_Vol[4]
ST1_Vol[3]
ST1_Vol[2]
ST1_Vol[1]
ST1_Vol[0]
6 HP_Gain[2]
HP_Gain[1]
HP_Gain[0]
ST2_Vol[4]
ST2_Vol[3]
ST2_Vol[2]
ST2_Vol[1]
ST2_Vol[0]
Bits labeled “Reserved” are reserved for future enhancements. They may not be written to as it may change the
function of the device. If read, these bits may assume any value.
The TPA2051D3 I2C address is 0xE0 (binary 11100000) for writing and 0xE1 (binary 11100001) for reading.
Refer to the General I2C Operation section for more details
Fault Register (Address: 0)
BIT
7
6
5
4
3
2
1
0
Function
Version[3]
Version[2]
Version[1]
Version[0]
Reserved
Spk_Fault
Thermal
Reset Value
0
16
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA2051D3
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