
(
)
J(MAX)
A(MAX)
DS(on)(MAX)
2
MAX
JA
DS(on)(MAX)
2
T
r
,
I
R
therefore,
150 C
50 C
r
13.6 m
12 A
51 C / W
q
-
=
°
-
°
=
W
°
OUT
VCC(MAX)
ON
LIM
VCC(MAX)
LIM
ON
C
V
t
if
P
I
V
I
therefore,
470 F 12 V
t
0.47 ms
12 A
=
>
=
ISS
FLT
ON
GATE
FLT
6 V C
t
,
I
therefore,
6 V 2040 pF
t
0.47 ms
1.08 ms
20 A
=
+
=
+
=
SLVSAL3B
– MARCH 2011 – REVISED MAY 2011
Next select the on resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage
greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a
maximum rDS(on) of 11.67 m is required. Also consider the effect of rDS(on) upon the maximum operating
temperature TJ(MAX) of the MOSFET. Equation 4 computes the value of rDS(on)(MAX) at a junction temperature of TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other
temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 4. (4)
Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a
VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During
normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the
MOSFET equates to 0.24 W and a 9.6
°C rise in junction temperature. This is well within the data sheet limits for
the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power.
The power handling capability of the MOSFET must be checked during fault conditions.
STEP 3. Choose Output Voltage Rising Time, tON, CT
The maximum output voltage rise time, tON, set by the timer capacitor CT must suffice to fully charge the load
capacitance COUT without triggering the fault circuitry. Equation 5 defines tON, where VCC(MAX) is the maximum input power bus voltage value and ILIM is the current limit value.
(5)
The next step is to determine the minimum fault-timer period. In Equation 5, the output rise time, tON, is the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses
the difference between the input voltage and the gate voltage to determine if the TPS24700/1 is still in inrush
limit. The fault timer continues to run until VGATE rises 6 V above the input voltage (for VVCC = 12 V). Some
additional time must be added to the total time to account for this additional gate voltage rising. The minimum
(6)
where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of TPS24700, or
20
μA. Using the example parameters in
Equation 6 and the CSD16403Q5 data sheet leads to a minimum fault
time of 1.08 ms. This time is derived considering the tolerances of COUT, CISS, ILIM, IGATE, COUT, and VVCC. The
fault timer must be set to a value higher than 1.08 ms to avoid turning off during start-up, but lower than any
maximum fault time limit determined by the device SOA curve.
There is a maximum time limit set by the SOA curve of the MOSFET. Referring to
Figure 31, which shows the
Copyright
2011, Texas Instruments Incorporated
19