
SLVSAL3B
– MARCH 2011 – REVISED MAY 2011
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1
exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-k
Ω resistor in series with CG is
recommended. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is
not necessary.
Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1
μF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the
low-impedance power bus when inserted. This stresses the connector contacts and causes a brief voltage sag
on the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1
μF) are often tolerable in these systems.
Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
Layout Considerations
TPS24700/1 applications require careful attention to layout to ensure proper performance and to minimize
susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list
deserves first consideration:
Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND.
Traces to VCC and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin
connections should be used at the points of contact with RSENSE. (see Figure 33). Power path connections should be as short as possible and sized to carry at least twice the full load current,
more if possible.
The device dissipates low power, so soldering the thermal pad to the board is not a requirement. However,
doing so improves thermal performance and reduces susceptibility to noise.
Protection devices such as snubbers, TVS, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, the
protection Schottky diode shown in the application diagram on the front page of the data sheet should be
physically close to the OUT pin.
22
Copyright
2011, Texas Instruments Incorporated