
SLVSAL3B
– MARCH 2011 – REVISED MAY 2011
Figure 29. Latch After Overload Fault
PGb AND TIMER OPERATIONS
The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M1. PGb
is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging.
PGb goes active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients
in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream
converter from demanding full current before the current-limit engine allows the MOSFET to conduct the full
current set by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The
pullup resistor shown on the PGb pin in the typical application diagram (front page) is illustrative only; the actual
connection to the converter depends on the application. The PGb pin may indicate that inrush has ended before
the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full
operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to ensure
that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV. After the
hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the
drain-to-source voltage of MOSFET M1 exceeds its upper threshold of 340 mV, which presents the downstream
converters a warning flag. This flag may occur as a result of overload fault, output short fault, high die
temperature, or the GATE shutdown by UVLO and EN.
The fault-timer defines an allowed period during which the load current can exceed the programmed current limit
(but not the fast-trip threshold). The fault timer starts when a current of approximately 10
μA begins to flow into
the external capacitor, CT, and ends when the voltage of CT reaches TIMER upper threshold, i.e., 1.35 V. The
fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The length of
the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins to count
under any of the following three conditions:
In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is enabled.
TIMER begins to sink current from the timer capacitor, CT when V(GATE–VCC) exceeds the timer activation
voltage (see the Inrush Operation section). If V(GATE–VCC) does not reach the timer activation voltage before
TIMER reaches 1.35 V, then the TPS24700/1 disables the external MOSFET M1. After the MOSFET turns
off, the timer goes into either latch mode (TPS24700) or retry mode (TPS24701).
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2011, Texas Instruments Incorporated