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參數資料
| 型號： | TPS24711DGSR |
| 廠商： | Texas Instruments |
| 文件頁數： | 21/34頁 |
| 文件大?。?/td> | 2792K |
| 描述： | IC CTRLR HOT SWAP 2.5-18V 10MSOP |
| 標準包裝： | 1 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電流限制： | 可調 |
| 電源電壓： | 2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | 296-28562-6 |
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TPS24710,TPS24711
TPS24712,TPS24713
www.ti.com
SLVSAL2E JANUARY 2011REVISED NOVEMBER 2013
activation voltage (see the Inrush Operation section). If V
(GATE VCC)
does not reach the timer activation
voltage before TIMER reaches 1.35 V, then the TPS24710/11/12/13 disables the external MOSFET M
1
. After
the MOSFET turns off, the timer goes into either latch mode (TPS24710/12) or retry mode (TPS24711/13).
2. In an overload fault, TIMER begins to source current to the timer capacitor, C
T
, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, C
T
, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, C
T
, when the load current
exceeds the programmed current limits following a fast-trip shutdown of M
1
. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C
T
, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or
retry mode (TPS24711/13).
If the fault current drops below the programmed current limit within the fault timer period, V
TIMER
decreases and
the pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode (TPS24710/12) and retry mode (TPS24711/13). If the
timer capacitor reaches the upper threshold of 1.35 V, then:
" In latch mode, the GATE remains low and the TIMER pin continues to charge and discharge the attached
capacitor periodically until TPS24710/12 is disabled by UVLO or EN as shown in Figure 33.
" In retry mode, TIMER charges and discharges C
T
between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24711/13 attempts to re-start. The TIMER pin is pulled
to GND at the end of the 16
th
cycle of charging and discharging and then ramps from 0 V to 1.35 V for the
initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload
fault is removed or the TPS24711/13 is disabled by UVLO or EN.
OVERTEMPERATURE SHUTDOWN
The TPS24710/11/12/13 includes a built-in overtemperature shutdown circuit designed to disable the gate driver
if the die temperature exceeds approximately 140癈. An overtemperature condition also causes the FLT, PG,
FLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has
fallen approximately 10癈.
START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN
The connection and disconnection between a load and the system bus are controlled by turning on and turning
off the MOSFET, M
1
.
The TPS24710/11/12/13 has two ways to turn on MOSFET M
1
:
1. Increasing V
VCC
above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M
1
.
2. Increasing EN above its upper threshold while V
VCC
is already higher than UVLO upper threshold sources
current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M
1
.
The EN pin can be used to start up the TPS24710/11/12/13 at a selected input voltage V
VCC
.
To isolate the load from the system bus, the GATE pin sinks current and pulls the gate of MOSFET M
1
low. The
MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit
threshold, hard short at load, or OTSD. Three separate conditions pull down the GATE pin:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
The fault timer expires during an overload current fault (V
SENSE
> 25 mV).
V
EN
is below its falling threshold.
V
VCC
drops below the UVLO threshold.
2. GATE is pulled down by a 1-A current source for 13.5 祍 when a hard output short circuit occurs and V
(VCC
SENSE)
is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-k& resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
Copyright ?20112013, Texas Instruments Incorporated
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Product Folder Links: TPS24710 TPS24711 TPS24712 TPS24713
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