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參數資料
型號: TPS24711DGSR
廠商: Texas Instruments
文件頁數: 9/34頁
文件大小: 2792K
描述: IC CTRLR HOT SWAP 2.5-18V 10MSOP
標準包裝: 1
類型: 熱交換控制器
應用: 通用
內部開關:
電流限制: 可調
電源電壓: 2.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-MSOP
包裝: 標準包裝
其它名稱: 296-28562-6
T
FLT
10 A
=
t
?/DIV>
LIM
EN  E
25 mV
=
R
J(MAX)
C(MAX)
LIM
窲C(MAX)
T
T
<
R
-
TPS24710,TPS24711
TPS24712,TPS24713
www.ti.com
SLVSAL2E JANUARY 2011REVISED NOVEMBER 2013
(2)
where  T
J(MAX)
is  the  maximum  desired  transient  junction  temperature  and  T
C(MAX)
is  the  maximum  case
temperature prior to a start or restart. R
鐹C(MAX)
is the junction-to-case thermal impedance of the pass MOSFET
M
1
in units of 癈/W. Both T
J(MAX)
and T
C(MAX)
are in 癈.
SENSE: This pin connects to the negative terminal of R
SENSE
. It provides a means of sensing the voltage across
this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit
I
LIM
is set by Equation 3.
(3)
A fast trip shutdown occurs when V
(VCC  VSENSE)
exceeds 60 mV.
TIMER: A capacitor C
T
connected from the TIMER pin to GND determines the overload fault timing. TIMER
sources 10 礎 when an overload is present, and discharges C
T
at 10 礎 otherwise. M
1
is turned off when V
TIMER
reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period
before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure
proper operation of the fault timer. The value of C
T
can be calculated from the desired fault time t
FLT
, using
Equation 4.
(4)
The latch mode (TPS24710/12) or the retry mode (TPS24711/13) occurs if the load current exceeds the current
limit threshold or the fast-trip shutdown threshold, While in latch mode, the TIMER pin continues to charge and
discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles
of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the
16
th
cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, C
T
,
can also be discharged to GND during latch mode or retry mode by a 2-mA current source whenever any of the
following occurs:
"   V
EN
is below its falling threshold.
"   V
VCC
drops below the UVLO threshold.
VCC: This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves
as an input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the
integrated circuit should connect directly to the positive terminal of R
SENSE
to minimize the voltage sensing error.
Bypass capacitor C
1
, shown in the typical application diagram on the front page, should be connected to the
positive terminal of R
SENSE
. A capacitance of at least 10 nF is recommended.
Copyright ?20112013, Texas Instruments Incorporated
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9
Product Folder Links: TPS24710  TPS24711 TPS24712  TPS24713
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