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參數(shù)資料
型號: TPS24711DGSR
廠商: Texas Instruments
文件頁數(shù): 26/34頁
文件大小: 2792K
描述: IC CTRLR HOT SWAP 2.5-18V 10MSOP
標(biāo)準(zhǔn)包裝: 1
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電流限制: 可調(diào)
電源電壓: 2.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 296-28562-6
Partof
TPS2471x
M
1
ToLoad
GND
GATE
romSource
R
GATE
1k
C
GATE
-
I
30  A
GATE
GATE
GATE
RS
t
I
C
V
?/DIV>
?/DIV>
D
=
?/DIV>
-
?/DIV>
?/DIV>
TPS24710,TPS24711
TPS24712,TPS24713
SLVSAL2E JANUARY 2011REVISED NOVEMBER 2013
www.ti.com
To select the gate capacitance, use Equation 15. I
GATE
is the nominal gate charge current. This equation
assumes that the MOSFET C
GD
is the controlling element as the gate and output voltage rise. C
GD
is non-linear
with applied V
DG
. An averaged estimate may be made using the MOSFET V
GS
vs Q
G
curve. Divide the charge
accumulated during the plateau region by the plateau V
GS
to get C
RS
.
(15)
Figure 36. Gate Capacitor (dV/dt) Control Inrush Mode.
ADDITIONAL DESIGN CONSIDERATIONS
Use of PG/PGb
Use the PG/PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow C
OUT
to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS24710/11/12/13 output characteristic and the dc/dc converter input characteristic if
the converter starts while C
OUT
is still charging; the PG/PGb pin is one way to avoid this
Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
Gate Clamp Diode
The TPS24710/11/12/13 has a relatively well-regulated gate voltage of 12 V to 15.5 V with a supply voltage V
VCC
higher than 4 V. A small clamp Zener from gate to source of M
1
is recommended if V
GS
of M
1
is rated below 12
V. A series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output
capacitance from discharging through the gate driver to ground.
High-Gate-Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M
1
exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-k?resistor in series with C
GATE
is
recommended (see Figure 36). If the series R-C combination is used for MOSFETs with C
ISS
less than 3000 pF,
then a Zener diode is not necessary.
26
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Copyright ?20112013, Texas Instruments Incorporated
Product Folder Links: TPS24710  TPS24711 TPS24712  TPS24713
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