
6
RETRY
T
=C
19 6
10
.
SLUSA65A – JULY 2010 – REVISED AUGUST 2010
www.ti.com
Adding External GATE-OUT Capacitance
Avoid directly placing ceramic capacitors directly across M1 gate to source when bypassing for ESD or noise is
desired. Add some small resistance in series with the capacitor if absolutely required. If the resistance is not
present, the added phase shift may encourage high frequency oscillation of the combined input and output L-C
circuits during startup conditions.
High Gate Capacitance Applications
If OUT falls very rapidly during a fault, the FET VGS can be driven high by the CGD - CGS voltage divider of
(VSENSE - VOUT). Given enough capacitance and dv/dt, the internal 14-V GATE to OUT clamp may not have the
capability to fully control the voltage. An external gate clamp Zener diode may be required to protect the FET if
this is the case.
When gate capacitor dV/dT control is used, a 1-k
resistor in series with CG is recommended, as shown in
Output Short Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to varying results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet since every setup differs.
Applications Using the Retry Feature (TPS2493)
Applications using the retry feature may want to estimate fault retry time. The TPS2493 will retry (enable M1 to
attempt turn on) once for every 16 timer charge/discharge cycles (15 cycles between 1 V and 4 V, 1 cycle
between 0 V and 4 V).
(25)
M1 Selection
Use of a power FET in the linear region places large, long term stresses on the distributed junction. FETs whose
safe operating area (SOA) curves display multiple slopes on the same line (e.g. a line whose time parameter is a
constant) in the region of high voltage and low current generally are susceptible to secondary breakdown and are
where the line at 10 ms shows no breaks in slope. The best device for the application is not always the lowest
RDSON device.
Layout Considerations
Good layout practice places the power devices D1, RSENSE, M1, and CO so power flows in a sequential, linear
fashion. A ground plane under the power and the TPS2492/93 is desirable. The TPS2492/93 should be placed
close to the sense resistor and FET using a Kelvin type connection to achieve accurate current sensing across
RSENSE. A low-impedance GND connection is required because the TPS2492/93 can momentarily sink upwards
of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the GATE trace
length short. The PROG, TIMER, OV, and UVEN pins have high input impedances, therefore keep their input
leads short. Oversize power traces and power device connections to assure low voltage drop and good thermal
performance.
26
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