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參數資料
| 型號： | TPS40075RHLTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | PLASTIC, QFN-20 |
| 文件頁數： | 14/44頁 |
| 文件大?。?/td> | 806K |
| 代理商： | TPS40075RHLTG4 |
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DIFFERENTIAL SENSE AMPLIFIER
SYNCHRONIZATION
POWERGOOD OPERATION
PRE-BIASED OUTPUTS
SHUTDOWN AND SEQUENCING
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The TPS40075 has an on board differential amplifier intended for use as a remote sensing amplifier for the
output voltage. Use of this amplifier for remote sensing eliminates load regulation issues due to voltage drops
that occur between the converter and the actual point of load. The amplifier is powered from the DBP pin and
can be used to monitor output voltages up to 6 V with a DBP voltage of 8 V. For lower DBP voltages, the sense
amplifier can be used to monitor output voltages up to 2-V below the DBP voltage. The internal resistors used to
configure the amplifier for unity gain match each other closely, but their absolute values can vary as much as
30%, so adding external resistance to alter the gain is not accurate in a production environment.
The SYNC pin accepts logic level signals and is used to synchronize the TPS40075 to an external clock source.
Synchronization occurs on the rising edge of the signal at the SYNC pin. There is a fixed delay of approximately
300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high-side FET. The pin
may be left floating in this function is not used, or it may be connected to GND. The frequency of the external
clock must be greater than the free running frequency of the device as set by the resistor on the RT pin (RRT).
This pin requires a totem pole drive, or open collector/drain if pull up resistor to either LVBP or a separate supply
between 2.5 V and 5 V is used. Synchronization does not affect the modulator gain due to the voltage feed
forward circuitry. The programmable UVLO thresholds are affected by synchronization. The thresholds are
shifted by the ratio of the sync frequency to the free running frequency of the converter. For example,
synchronizing to a frequency 20% higher than the free running frequency results in the programmable UVLO
thresholds shifting up 20% from their calculated free run values. The synchronization frequency should be kept
less than 1.5 times the free run frequency for best performance, although higher multiples can be used.
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5 V)
Soft-start is active (V
VSS < 3.5 V)
V
FB < 0.63 V
V
FB > 0.77 V
Programmable UVLO condition not satisfied (V
IN below programmed level)
Overcurrent condition exists
Die temperature is greater than 165°C
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the
output. Since synchronous buck converters inherently sink current some method of overcoming this characteristic
must be employed. Applications that require this operation are typically power rails for a multi supply processor
or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn on until there the
output voltage commanded by the start up ramp is higher than the pre-existing output voltage. This is detected
by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller uses a
closed loop startup, the first output pulse from the PWM does not occur until the output voltage is commanded to
be higher than the pre-existing voltage. This effectively limits the controller to sourcing current only during the
startup sequence.
If the pre-existing voltage is higher that the intended regulation point for the output of the converter, the converter
starts and sinks current when the soft-start time has completed
The TPS40075 can be shut down by pulling the SS pin to a level below 250 mV. Pulling the pin low resets the
internal pre-bias circuitry to ensure that the converter does not damage sensitive loads.
Copyright 2006–2007, Texas Instruments Incorporated
21
Product Folder Link(s) :TPS40075
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