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參數資料
| 型號： | TPS40075RHLTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | PLASTIC, QFN-20 |
| 文件頁數： | 8/44頁 |
| 文件大小： | 806K |
| 代理商： | TPS40075RHLTG4 |
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R t
0.2 V
f
SW
Q
g(TOT) ) IIDD
(1)
C u
V
VIN * 8 V
R
SR
(2)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
R
T +
1
f
SW(kHz)
17.82
10*6
* 23
kW
(3)
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO FUNCTION
R
KFF + 0.131
R
T
V
UVLO(on) * 1.61
10*3
V
UVLO(on)
2
) 1.886
V
UVLO * 1.363 * 0.02
R
T * 4.87
10*5
R2
T
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
where
V
VIN is the final value of the input voltage ramp
f
SW is the switching frequency
Q
g(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)
I
IDD is the TPS40075 input current (3.5 mA maximum)
SR is the maximum allowed slew rate [12 ×104] (V/s)
The TPS40075 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as
the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching
frequency of the clock oscillator. The clock frequency is related to RT by:
The ramp generator circuit provides the actual ramp used by the PWM comparator and provides voltage
feed-forward by varying the PWM ramp slope as the line voltage changes. As the input voltage to the converter
increases, the slope of the PWM ramp increase by a proportionate amount. The programmable UVLO circuit
works by monitoring the level reached by the PWM ramp during a clock cycle. The PWM ramp must reach
approximately 1 V in amplitude during a clock cycle, or the converter is not be allowed to start. This
programmable UVLO point is set via a single resistor (RKFF) connected from KFF to VDD. RKFF , VSTART and RRT
are related by (approximately)
(4)
where
V
UVLO(on) is in volts
R
KFF and RT are in k
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up
±15% from this number. Figure 19 through Figure 21 show the typical relationship of VUVLO(on), VUVLO(off) and RKFF
at three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For
example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts
down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice
the startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that with
this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times
the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the
desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a
5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 22 shows the theoretical
maximum duty cycle (typical) for various programmed startup voltages
If the programmable UVLO voltage is set below 6.5V nominal, a possibility exists that the part may enter factory
test mode when powered down. This can cause an undesired output rise as power is removed from the
converter. To prevent this from happening, connect a 330 k
resistor from SS to GND. An example of this can be
seen in Figure 37
16
Copyright 2006–2007, Texas Instruments Incorporated
Product Folder Link(s) :TPS40075
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