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參數(shù)資料
| 型號： | TPS40075RHLTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | PLASTIC, QFN-20 |
| 文件頁數(shù)： | 16/44頁 |
| 文件大小： | 806K |
| 代理商： | TPS40075RHLTG4 |
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GROUNDING AND BOARD LAYOUT
SYNCHRONOUS RECTIFIER CONTROL
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The TPS40075 provides separate signal ground (GND) and power ground (PGND) pins. Care should be given to
proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (DBP), and the input capacitor should be connected to PGND plane.
Sensitive nodes such as the FB resistor divider and RT should be connected to the GND plane. The GND plane
should only make a single point connection to the PGND plane. It is suggested that the GND pin be tied to the
copper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as well and
make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the
GND pin.
Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible
to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout
practices results in sub-optimal operation.
Table 2 describes the state of the rectifier MOSFET control under various operating conditions.
Table 2. Synchronous Rectifier MOSFET States
SYNCHRONOUS RECTIFIER OPERATION DURING
FAULT
SOFT-START
NORMAL
(FAULT RECOVERY IS SAME
OVERVOLTAGE
AS SOFT-START)
Off until first high-side pulse is
Turns off at the start of a new
Turns OFF only at start of next
detected, then on when high-side
cycle. Turns on when the
OFF
cycle ON if duty cycle is > 0
MOSFET is off
high-side MOSFET is turned off
For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.
Copyright 2006–2007, Texas Instruments Incorporated
23
Product Folder Link(s) :TPS40075
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