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參數資料
型號: TPS51220ARTVR
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩壓器
英文描述: DUAL SWITCHING CONTROLLER, 333 kHz SWITCHING FREQ-MAX, PQCC32
封裝: 5 X 5 MM, PLASTIC, QFN-32
文件頁數: 20/53頁
文件大?。?/td> 1380K
代理商: TPS51220ARTVR
I
OCL(DC) + IOCL(PEAK) * 0.5
I
IND(RIPPLE)
I
OCL(PEAK) +
V
OCL
R
SENSE
www.ti.com
SLUS897D – DECEMBER 2008 – REVISED FEBRUARY 2010
ADAPTIVE ZERO CROSSING
TPS51220A has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.
CURRENT PROTECTION
TPS51220A has cycle-by-cycle overcurrent limiting control. If the inductor current becomes larger than the
overcurrent trip level, TPS51220A turns off high-side MOSFET, turns on low-side MOSFET and waits for the next
clock cycle.
IOCL(PEAK) sets peak level of the inductor current. Thus, the dc load current at overcurrent threshold, IOCL(DC), can
be calculated as follows;
(5)
where
RSENSE is resistance of current sensing device
V(OCL) is the overcurrent trip threshold voltage which is determined by TRIP pin voltages as shown in Table 3
(6)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down, and it ultimately crosses the undervoltage protection threshold and shutdown.
Table 3. OCL Trip and Discharge Selection
TRIP
GND
VREF2
VREG3
VREG5
V(OCL) (OCL TRIP VOLTAGE)
V(OCL-ULV) (ULTRA-LOW VOLTAGE)
V(OCL-LV) (LOW VOLTAGE)
DISCHARGE
Enable
Disable
Enable
POWERGOOD
The TPS51220A has powergood output for both switcher channels. The powergood function is activated after
softstart has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the powergood signal becomes high after 1ms internal delay. If the output voltage goes
outside of ±10% of the target value, the powergood signal becomes low after 1.5ms internal delay. Apply voltage
should be less than 6V and the recommended pull-up resistance value is from 100k
to 1M.
OUTPUT DISCHARGE CONTROL
The TPS51220A discharges output when ENx is low. The TPS51220A discharges outputs using an internal
MOSFET which is connected to CSNx and GND. The current capability of these MOSFETs is limited to
discharge the output capacitor slowly. If ENx becomes high during discharge, MOSFETs are turning off, and
some output voltage remains. SMPS changes over to soft-start. The PWM initiates after the target voltage
overtakes the remaining output voltage. This function can be disabled as shown in Table 3.
Copyright 2008–2010, Texas Instruments Incorporated
27
Product Folder Link(s) :TPS51220A
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相關代理商/技術參數
參數描述
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