
3.3 V, 10 mA LDO (VREG3)
2.0-V, 100
A Sink/ Source Reference (VREF2)
5.0-V, 100 mA LDO (VREG5)
VREG5 SWITCHOVER
BASIC PWM OPERATIONS
PWM FREQUENCY CONTROL
sw[kHz] + 1
105
RF[kW]
(1)
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A 3.3-V, 10mA, linear regulator is integrated in the TPS51221. This LDO services some of the analog supply rail
for the IC and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-
F (at least 1-F), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND, adjacent to the
IC.
This voltage is used for the reference of the loop compensation network. Apply a 0.22-
F (at least 0.1-F), high
quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND, adjacent to the IC.
A 5.0-V, 100-mA linear regulator is integrated in the TPS51221. This LDO services the main analog supply rail
for the IC and provides current for gate drivers until switch-over function becomes enabled. Apply 10-
F (at least
4.7-
F), high quality X5R or X7R ceramic capacitor from VREG5 to (power) GND, adjacent to the IC.
When EN1 is high, PGOOD1 indicates GOOD and more than 4.7-V voltage is applied to V5SW, the internal
5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after A 7.7ms delay. When the
V5SW voltage becomes lower than 4.5 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is
turned off and the internal 5V-LDO resumes immediately.
The main control loop of the SMPS is designed as a fixed-frequency, peak current mode pulse width modulation
(PWM) controller. It can achieve stable operation in any type of capacitors, including low ESR capacitor(s) such
as ceramic or specialty polymer capacitors.
The TPS51221 SMPS uses the output voltage information and the inductor current information to regulate the
output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the internal
1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The inductor
current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage goes down, the TPS51221 increases the target inductor current to raise the output voltage. On
the other hand, if the output voltage goes up the TPS51221 decreases the target inductor current to reduce the
output voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ON state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current reaches the target value—which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The
high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the
controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each
OFF state to keep the conduction loss minimum.
TPS51221 has a fixed frequency control scheme with 180° phase shift. The switching can be determined by an
external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1:The TPS51221 can also synchronize to the external clock, of more than 2.5-V amplitude, by applying the signal
to RF pin. The set timing of the channel-1 initiates at the raising edge (1.3V typ) of the clock, and channel-2
initiates at the falling edge (1.1V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
When the external clock synchronization is selected, the following conditions are required.
Remove RF resistor
Add clock signal before EN1 or EN2 turning on
Copyright 2007–2009, Texas Instruments Incorporated
21