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參數資料
| 型號： | TPS5211PWPR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 13/29頁 |
| 文件大小： | 500K |
| 代理商： | TPS5211PWPR |
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TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating virtual-junction temperature range,
V
CC
= 12 V, I
DRV
= 0 A (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSENSE to HIGHDR or
LOWDR (excluding dead-
time)
1.3 V
≤
VVREF
≤
3.5 V, 10 mV overdrive
(see Note 3)
150
250
ns
Propagation delay
Pro agation delay
OCP comparator
1
OVP comparator
See Note 3
1
μ
s
PWRGD comparator
1
SLOWST comparator
Overdrive = 10 mV (see Note 3)
560
900
ns
Rise time
HIGHDR output
CL = 9 nF,
VBOOTLO = 0 V,
CL = 9 nF,
TJ = 125
°
C
CL = 9 nF,
VBOOTLO = 0 V,
CL = 9 nF,
TJ = 125
°
C
VBOOT = 6.5 V,
TJ = 125
°
C
VDRV = 6.5 V,
60
ns
LOWDR output
60
Fall time
HIGHDR output
VBOOT = 6.5 V,
TJ = 125
°
C
VDRV = 6.5 V,
60
ns
LOWDR output
60
Deglitch time (Includes
comparator propagation
delay)
OCP
See Note 3
2
5
μ
s
OVP
2
5
VHISENSE = 12 V,
VIOUTLO pulsed from 12 V to 11.9 V,
100 ns rise/fall times
(see Note 3)
2
Response time
High-side VDS sensing
VHISENSE = 4.5 V,
VIOUTLO pulsed from 4.5 V to 4.4 V,
100 ns rise/fall times (see Note 3)
3
μ
s
VHISENSE = 3 V,
VIOUTLO pulsed from 3 V to 2.9 V,
100 ns rise/fall times (see Note 3)
3
Short-circuit protection
rising-edge delay
SCP
LOSENSE = 0 V (see Note 3)
300
500
ns
Turn-on/turn-off delay
VDS sensing sample/hold
switch
3 V
≤
VHISENSE
≤
11 V,
VLOSENSE = VHISENSE (see Note 3)
30
100
ns
Crossover delay time
LOWDR to HIGHDRV, and
LOHIB to LOWDR
See Note 3
30
100
ns
Prefilter pole frequency
Hysteretic comparator
See Note 3
5
MHz
Propagation delay
NOTE 3: This parameter is ensured by design and is not production tested.
LODRV
See Note 3
400
ns
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