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參數資料
| 型號： | TPS5211PWPR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 22/29頁 |
| 文件大小： | 500K |
| 代理商： | TPS5211PWPR |
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TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
hysteresis voltage
A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the output which the
input comparator uses for sensing. Once selected, the TPS5210 hysteresis is proportional to the reference
voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same percentage of
Vref. The actual output ripple voltage is the combination of the hysteresis voltage, overshoot caused by internal
delays, and the output capacitor characteristics. Figure 20 shows the hysteresis window voltage (V
HI
to V
LO
)
and the output voltage ripple (V
MAX
to V
MIN
). Since the output current from VREFB should be less than 500
μ
A,
the total divider resistance (R5 + R6) should be greater than 7 K
. The hysteresis voltage should be no greater
than 60 mV so R6 will dominate the divider.
R5
R6
VHSYT
VREFB
Hysteresis Window = 2
×
VR5
Figure 19. Hysteresis Divider Circuit
VO
VMAX
VHI
VMIN
VREF
VLO
t
Figure 20. Output Ripple
The upper divider resistor, R5, is calculated using:
(
)
( )
(
)
6
100
2
6
2
5
0
R
V
R
Window
Hysteresis
VREFB
Window
Hysteresis
–
R
HYST
×
×
×
×
=
Where Hysteresis Window = the desired peak-to-peak hysteresis voltage.
VREFB = selected reference voltage.
V
HYST
(%) = [(Hysteresis Window)/VREFB] * 100 < V
O(Ripple)(P–P)
(%)
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