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參數資料
| 型號： | TPS5211PWPR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 4/29頁 |
| 文件大?。?/td> | 500K |
| 代理商： | TPS5211PWPR |
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TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
V
REF
The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to V
CC
. The VID codes conform
to the Intel VRM 8.3 DC-DC Converter Specificationfor voltage settings between 1.8 V and 3.5 V, and they are
decremented by 50 mV, down to 1.3 V, for the lower VID settings. Voltages higher than V
REF
can be implemented
using an external divider. Refer to Table 1 for the VID code settings. The output voltage of the VID network, V
REF
,
is within
±
1% of the nominal setting over the VID range of 1.3 V to 25 V, including a junction temperature range
of 5
°
C to +125
°
C, and a V
CC
supply voltage range of 11.4 V to 12.6 V. The output of the reference/VID network
is indirectly brought out through a buffer to the V
REFB
pin. The voltage on this pin will be within 2% of V
REF
. It
is not recommended to drive loads with V
REFB
, other than setting the hysteresis of the hysteretic comparator,
because the current drawn from V
REFB
sets the charging current for the slowstart capacitor. Refer to the
slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on V
REF
. The 2 external resistors form a resistor divider from V
REFB
to ANAGND, with the output voltage connecting to the V
HYST
pin. The hysteresis of the comparator will be equal
to twice the voltage differencebetween the V
REFB
and V
HYST
pins. The propagation delay from the comparator
inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or V
CC
.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-
switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033
μ
F and 0.1
μ
F. Internal logic controls
the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
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