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參數資料
| 型號： | TPS5211PWPR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 5/29頁 |
| 文件大小： | 500K |
| 代理商： | TPS5211PWPR |
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TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
droop compensation
The droop compensation network reduces the load transient overshoot/undershoot on V
O
, relative to V
REF
. V
O
is programmed to a voltage greater than V
REF
by an external resistor divider from V
O
to VSENSE to reduce the
undershoot on V
O
during a low-to-high load transient. The overshoot during a high-to-low load transient is
reduced by subtracting the voltage on DROOP from V
REF
. The voltage on IOUT is divided with an external
resistor divider, and connected to DROOP.
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
V
CC
undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the V
CC
supply is below the 10-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When V
CC
exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which V
O
powers up. A capacitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of C
slowst
is proportional to the reference voltage. By making the charging
current proportional to V
REF
, the power-up time for V
O
will be independent of V
REF
. Thus, C
SLOWST
can remain
the same value for all VID settings. The slowstart charging current is determined by the following equation:
I
slowstart
= I(V
REFB
) / 5 (amps)
Where I(V
REFB
) is the current flowing out of V
REFB
.
It is recommended that no additional loads be connected to V
REFB
, other than the resistor divider for setting the
hysteresis voltage. The maximum current that can be sourced by the V
REFB
circuit is 500
μ
A
.
The equation for
setting the slowstart time is:
t
SLOWST
= 5
×
C
SLOWST
×
R
VREFB
(seconds)
Where R
VREFB
is the total external resistance from V
REFB
to ANAGND.
power good
The power-good circuit monitors for an undervoltage condition on V
O
. If V
O
is 7% below V
REF
, then the PWRGD
pin is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors V
O
for an overvoltage condition. If V
O
is 15% above V
REF
,
then a fault latch is set and both output drivers are turned off. The latch will remain set until V
CC
goes below the
undervoltage lockout value. A 3-
μ
s deglitch timer is included for noise immunity. Refer to the
LODRV
section
for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
high-side power FET.
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