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參數資料
| 型號： | TPS53851RHHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | SWITCHING CONTROLLER, PQCC36 |
| 封裝： | PLASTIC, VQFN-36 |
| 文件頁數： | 16/66頁 |
| 文件大小： | 1264K |
| 代理商： | TPS53851RHHT |
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PWM A
1
2
3
4
5
6
7
8
9
EXT CLKA
EXT CLKS
1
2
3
4
5
6
7
8
1
11
10
3
2
PWM S
UDG06032
R
SET + VOUT
1
V
IN2
*
1
V
IN1
100 kW
www.ti.com
SLUS985 – DECEMBER 2009
Figure 5-7 shows a time slice of the two external clock possibilities and the resulting PWM signal. EXT
CLK-A is the continuous clock with no missing pulse and the PWM-A signal could be frequency
synchronized anywhere in the clock stream. The PWM signal is at 1/8 of the EXT CLK-A frequency. EXT
CLK-S is the external clock stream with a missing pulse every 8 cycles. The phasing of the PWM-S is
based on the voltage on the PHSEL pin. For PHSEL grounded, the PWM-S signal is shifted 90 degrees
from what would be the falling edge of the missing pulse as shown.
Figure 5-7. Synchronizing a Single Controller to an External Clock
5.22 SPLIT INPUT VOLTAGE OPERATION
It may be advantageous to operate a master controller’s power stages from VIN 1, different from the slave
controller(s) power stages, VIN 2 where VIN 1 > VIN 2. This enables the system designer to optimize the
current taken from the system input voltages. In order to balance the output currents, a programmed offset
is applied to ILIM2 of the slave controller(s). The voltage on this pin sets the offset current for channel 2.
The ramp offset is determined by a resistor, RSET, connected to the ILIM2 pin of the slave, and is given by:
(6)
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
23
Product Folder Link(s): TPS53851
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