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參數資料
型號: TPS53851RHHT
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩壓器
英文描述: SWITCHING CONTROLLER, PQCC36
封裝: PLASTIC, VQFN-36
文件頁數: 56/66頁
文件大小: 1264K
代理商: TPS53851RHHT
SLUS985 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 k, Pullup to BP5,
f SW = 300 kHz, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE AMPLIFIERS (CS1, CS2)
Differential input voltage
-60
60
mV
Input offset voltage
CS1, CS2, Trimmed
-2.0
0
2.0
mV
Ac
Gain transfer to PWM comparator
5 mV < VCS < 60 mV, VCSRT = 1.5 V
12
13
14
V/V
VICM
Input common mode(1)
0
5.8
V
CSA
Input bias current
100
nA
PWM COMPARATOR
VOFFSET
Input offset voltage
–3
3
mV
DIFFERENTIAL AMPLIFIER (DIFFO)
Gain
1.0 V < VOUT < 5.8 V
0.997
1
1.003
V/V
Input common mode range(1)
0
5.8
V
(VOUT – VVGSNS) = 2 V, VDIFFO > 1.98 V,
2
(VVDD – VOUT ) > 2 V
IDIFFOH
Output source current(1)
(VOUT – VVGSNS) = 2 V, VDIFFO > 2.02 V,
1
mA
(VVDD – VOUT) = 1 V
(VOUT –VVGSNS) = 2 V,
IDIFFOL
Output sink current(1)
2
VDIFFO > 2.02 V
BWDIFF
Unity gain bandwidth(1)
5
8
MHz
Input impedance, non inverting(1)
VOUT to GND
60
k
Input impedance, inverting(1)
GSNS to DIFFO
60
GATE DRIVERS
VBOOT1, VBOOT2 = 5 V, VSW1 = VSW2 = 0
RHDRV(on)
HDRV1, HDRV2 source on-resistance
V,
1
2
3
Sourcing 100 mA
VVREG = 5 V, VSW1 = VSW2 = 0 V,
RHDRV(off)
HDRV1, HDRV2 sink on-resistance
0.5
1.2
2
Sinking 100 mA
VVREG = 5 V, VSW1 = VSW2 = 0 V,
RLDRV(on)
LDRV1, LDRV2 source on-resistance
1
2
3
Sourcing 100 mA
VVREG = 5 V, VSW1 = VSW2 = 0 V,
RLDRV(off)
LDRV1, LDRV2 sink on-resistance
0.3
0.65
1
Sinking 100 mA
tRISE
HDRVx rise time(1)
CLOAD= 3.3 nF
25
75
tFALL
HDRVx fall time(1)
CLOAD= 3.3nF
25
75
tRISE
LDRVx rise time(1)
CLOAD= 3.3nF
25
75
ns
tFALL
LDRVx fall time(1)
CLOAD= 3.3nF
20
60
Minimum controllable on-time
CLOAD= 3.3nF
50
OUTPUT UNDERVOLTAGE FAULT
FB undervoltage threshold
VFB relative to VREF
-19%
-16.5%
-14%
Undervoltage delay(1)
3
μs
CURRENT LIMIT
IILIM
Output current
18.8
20
21.2
μA
POWER GOOD
VFBPG_H
PGOOD transition low threshold
VFB rising relative to VREF
10%
12.5%
15%
VFBPG_L
PGOOD transition low threshold
VFB falling relative to VREF
-15%
-12.5%
-10%
VFBPG(hyst) PGOOD trip hysteresis
2%
5%
tPGDLY
PGOOD delay(1)
10
μs
VPGL
Low-level output voltage, VOL
IPGOOD = 4 mA
0.35
0.4
V
IPGLK
PGOOD bias current
VPGOOD= 5.0 V
-2
1
2
μA
(1)
Ensured by design. Not 100% production tested.
6
DEVICE RATINGS
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS53851
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