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參數資料
| 型號： | TPS54320RHLR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | SWITCHING REGULATOR, 1320 kHz SWITCHING FREQ-MAX, PQCC14 |
| 封裝： | 3.50 X 3.50 MM, GREEN, PLASTIC, QFN-14 |
| 文件頁數： | 10/39頁 |
| 文件大?。?/td> | 1358K |
| 代理商： | TPS54320RHLR |
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VSENSE
COMP
VOUT
R8
R4
C4
C6
R9
Coea
Roea
gm
1300 mA/V
0.8 V
Power Stage
PH
RESR
CO
RL
b
a
c
12 A/V
SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010
www.ti.com
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart
after the hiccup time which is set for 16384 cycles. The hiccup mode helps to reduce the device power
dissipation under severe overcurrent conditions.
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C
typically.
Small Signal Model for Loop Response
Figure 30 shows an equivalent model for the device's control loop which can be modeled in a circuit simulation
program to check frequency response and transient responses. The error amplifier is a transconductance
amplifier with a gm of 1300mA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Roea (2.38 M
) and capacitor Coea (20.7 pF) model the open loop gain and frequency
response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of
the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the
overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the
appropriate load step amplitude and step rate in a time domain analysis.
Figure 30. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
compensation. The device's power stage can be approximated to a voltage controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage
transconductance (gmps) which is 12 A/V for the device. The DC gain of the power stage is the product of gmps
and the load resistance (RL), as shown in Equation 11 with resistive loads. As the load current increases, the DC
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 32.
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
18
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS54320
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