
2
Iout
pmod
Vout Co
p
=
× ×
×
f
1
2
zmod
RESR Co
p
=
× ×
×
f
2
ea
ps
c Vout Co
R4
gm
Vref gm
p ×
×
=
×
f
Vout Co
C4
Iout R4
×
=
×
1
2
C11
R8
c
p
=
× ×
× f
1
2
p
R4 C6
p
=
× ×
×
f
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SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010
Compensation Component Selection
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54320. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the
crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.
Type III compensation is used to achieve a high bandwidth, high phase margin design. This design targets a
crossover frequency (bandwidth) of 48kHz (1/10th of the switching frequency). Using
Equation 32 and
Equation 33, the power stage pole and zero are calculated at 6.46kHz and 1778kHz, respectively. For the output
capacitance, CO, use a derated value of 22.4 F.
(32)
(33)
Now the compensation components can be calculated. First, calculate the value for R4 which sets the gain of the
compensated network at the crossover frequency. Use
Equation 34 to determine the value of R4.
(34)
Next calculate the value of C4. Together with R4, C4 places a compensation zero at the modulator pole
frequency. Use
Equation 35 to determine the value of C4.
(35)
and 0.015F. The next
higher standard value for C4 is selected to give a compensation zero that is slightly lower in frequency than the
power stage pole.
In order to provide a zero around the crossover frequency to boost the phase at crossover, a capacitor (C11) is
added parallel to R8. The value of this capacitor is given by
Equation 36. The nearest standard value for C11 is
100pF.
(36)
Use of the feedforward capacitor, C11, creates a low AC impedance path from the output voltage to the VSENSE
input of the IC that can couple noise at the switching freqeuncy into the control loop. Use of a feedforward
capacitor is not recommended for high output voltage ripple designs (greater than 15 mV peak to peak at the
VSENSE input) operating at duty cycles of less than 30%. When using the feedforward capacitor, C11, always
limit the closed loop bandwidth to no more than 1/10th of the switching frequency, fsw.
An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series
combination of R4 and C4. The pole frequency is given by
Equation 37. This pole is set at roughly half of the
switching frequency (of 480 kHz) by use of a 330 pF capacitor for C6. This helps attenuate any high frequency
signals that might couple into the control loop.
(37)
Copyright 2010, Texas Instruments Incorporated
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