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參數資料
| 型號： | TRF5001GQE |
| 英文描述： | RECEIVER|BICMOS|BGA|80PIN|PLASTIC |
| 中文描述： | 接收機| BICMOS工藝| BGA封裝| 80腳|塑料 |
| 文件頁數： | 4/19頁 |
| 文件大小： | 258K |
| 代理商： | TRF5001GQE |
DATE AND TRACKING INFORMATION
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
B0
B1
B2
B3
CLK
CP_OUT
DATA
DSP_CLK
NO.
F9
G9
H9
J9
J8
A8
J7
E9
O
O
O
O
I
O
I
I/O
ADC bit 0 (LSB)
ADC bit 1
ADC bit 2
ADC bit 3 (MSB)
Clock signal from 3-wire interface
Charge pump output from PLL phase frequency detector (PFD)
Data signal from 3-wire interface
Clock to/from baseband
I = ADC sampling clock input
0 = internally generated sampling clock to ADC
EN
GND_ADC
GND_BUFFER
GND_DIG
GND_IF1
GND_IF2
GND_LNA1
J6
H6
H8
E8
H3
H4
C1
I
Enable signal from 3-wire interface
ADC ground
ADC buffer ground
Digital ground
IF ground
IF ground
GND_LNA2
D2
RF LNA ground
GND_LNA3
GND_PLLA
GND_RFMIX1
GND_RFMIX2
E1
B8
F2
H1
g ou d
Charge pump ground
RF mixer ground
GND_SUB
A2, G3,
H2
Substrate ground
GND_VCO
IF_IN+
IF_IN–
LNA_IN
NC
PLL_LOCK
RFMIX_OUT–
RFMIX_OUT+
SLEEP
TCXO
VAR_IN
VCC_BUFFER
VCC_IF
VCC_LNA
VCC_PLLA
VCC_RFMIX
VCC_VCO
VCO_TKC1
VCO_TKC2
VDD_ADC
VDD_PLLD
B7, B3
J3
J4
D1
A3
D9
G1
F1
A1
C9
A7
F8, G8
J2
B1
A9
J1
A5
A4
A6
J5
B9
VCO ground
IF amplifier input
IF amplifier input
RF LNA input
No connection
PLL lock detected
RF mixer output
RF mixer output
Sleep mode (RX blanking) enable
Reference oscillator input
VCO varactor input
ADC buffer power supply
IF power supply
RF LNA power supply
Charge pump power supply
RF mixer power supply
VCO power supply
VCO tank
VCO tank
ADC power supply
PLL power supply
I
I
I
O
O
O
I
I
I/O
I
I
I
I
I
I
I/O
I/O
I
I
P
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