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參數資料
| 型號： | TS83102G0BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152 |
| 文件頁數： | 31/60頁 |
| 文件大小： | 1510K |
| 代理商： | TS83102G0BCGL |
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37
0830E–BDC–06/07
e2v semiconductors SAS 2007
TS83102G0B
negligible. Consequently, the minimum values for TOD and TDR are never more than 100 ps apart. The
same is true for their maximum values.
However, the external TOD and TDR values can be dictated by the total digital data skews between
each TOD and TDR. These digital skews can include the MCM board, bonding wires and output line
length differences, as well as output termination impedance mismatches.
The external (on-board) skew effect has not been taken into account for the specification of TOD and
TDR minimum and maximum values.
13.1.4
Principle of Operation
The analog input is sampled on the rising edge of the external clock’s input (CLK/CLKB) after TA (aper-
ture delay). The digitized data is available after 4 clock periods’ latency (pipeline delay [TPD]) on the
clock’s rising edge, after a typical propagation delay TOD. The Data Ready differential output signal fre-
quency (DR/DRB) is half the external clock’s frequency. It switches at the same rate as the digital
outputs. The Data Ready output signal (DR/DRB) switches on the external clock’s falling edge after a
propagation delay TDR.
If TOD equals TDR, the rising edge (True-False) of the differential Data Ready signal is placed in the
middle of the Output Data Valid window. This gives maximum setup and hold times for external data
acquisition.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available
for initializing the differential Data Ready output signal (DR/DRB). This feature is mandatory in certain
applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Without Data
Ready signal initialization, it is impossible to store the output digital data in a defined order.
When used with e2v’s TS81102G0 1:4/8 8/10 bit DMUX, it is not necessary to initialize Data Ready, as
this device can start on either clock edge.
13.2
Principle of Data Ready Signal Control by DRRB Input Command
13.2.1
Data Ready Output Signal Reset
The Data Ready signal is reset on the DRRB input command’s falling edge, on the ECL logical low level
(-1.8V). DRRB may also be tied to V
EE = - 5V for the Data Ready output signal master reset. As long as
DRRB remains at a logical low level, (or tied to V
EE = - 5V), the Data Ready output remains at a logical
zero and is independent of the external free-running encoding clock.
The Data Ready output signal (DR/DRB) is reset to a logical zero after TRDR.
TRDR is measured between the -1.3V point of the DRRB input command’s falling edge and the zero
crossing point of the differential Data Ready output signal (DR/DRB).The Data Ready Reset command
may be a pulse of 1 ns minimum time width.
13.2.2
Data Ready Output Signal Restart
The Data Ready output signal restarts on the DRRB command’s rising edge, on the ECL logical high
level (-0.8V).
DRRB may also be grounded, or may float, for normal free-running of the Data Ready output signal. The
Data Ready signal’s restart sequence depends on the logical level of the external encoding clock, at a
DRRB rising edge instant:
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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