- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98293 > TS83102G0BCGL (E2V TECHNOLOGIES PLC) 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 PDF資料下載
參數(shù)資料
| 型號： | TS83102G0BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152 |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 1510K |
| 代理商： | TS83102G0BCGL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
42
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
13.6
Digital Outputs: Termination and Logic Compatibility
Each single-ended output of the TS83102G0B’s differential output buffers are internally 50
terminated,
and feature a 100
differential output impedance. The 50 resistors are connected to the VPLUSD dig-
ital power supply. The TS83102G0B output buffers are designed to drive 50
controlled impedance
lines properly terminated by a 50
resistor. A 10.5 mA bias current flowing alternately into one of the 50
resistors when switching, ensures a 0.25V
single-ended voltage drop across the resistor (0.5V differential).
Each single-ended output transmission line length must be kept identical (< 3 mm). Mismatches in the
differential line lengths may cause variations in the output differential common mode.
It is recommended to bypass the midpoint of the differential 100
termination with a 47 pF capacitor, so
as to avoid common mode perturbations in case of a slight mismatch in the differential output line
lengths.
See the recommended termination scenarios in Figures 46. and 47. below.
Note:
Since the output buffers feature a 100
differential output impedance, it is possible to directly drive high
the input impedance storing registers without terminating the 50
transmission lines. Timewise, this
means that the incident wave reflects at the 50
transmission line output and travels back to the 50 data
output buffer. Since the buffer output impedance is 50
, no
back reflection occurs and the output swing is doubled.
13.6.0.1
VPLUSD Digital Power Supply Settings
For differential ECL digital output levels: V
PLUSD should be supplied with -0.8V (or connected to
ground via a 5
resistor to ensure the -0.8 voltage drop).
For the LVDS digital output logic compatibility: V
PLUSD should be tied to 1.45V
(±75 mV).
If used with the TS81102G0 DMUX, V
PLUSD can be set to ground.
13.6.1
ECL Differential Output Termination Configurations
Figure 13-7. 50
Terminated Differential Outputs (Recommended)
10.5 mA
Zc = 50
OUT
VPLUSD = -0.8V
Zc = 50
50
50
OUTB
50
50
VOL typ = -1.17V
VOH typ = -0.94V
Differential Output Swing:
±0.23V = 0.46 Vpp
Common Mode Level = -1.05V
47 pF
相關PDF資料 |
PDF描述 |
|---|---|
| TS83110CZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110MZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110VZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110MZB/T | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28 |
| TS83110VS | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。