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參數資料
| 型號： | TS8387VF_ |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 22/38頁 |
| 文件大?。?/td> | 617K |
| 代理商： | TS8387VF_ |
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TS8387
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Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the
active inputs.
The analog inputs and clock inputs of the TS8387 chip have been surrounded by ground pads, which must be directly
connected to the external ground plane.
7.6.
DIGITAL OUTPUTS
The TS8387 differential output buffers are internally 75 ohms loaded. The 75 ohms resistors are connected to the digital
ground pads through a –0.8v level shift diode.
(See Figure below).
The TS8387 output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines
or coaxial cables.
An 11 mA bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 V voltage
drop across the resistor.
Therefore,the single ended output voltages vary approximately between –0.8V and –1.625V, ( outputs unterminated ),
around –1.2V common mode voltage.
Three possible line driving and back–termination scenarios are proposed :
1 ) 75 Ohms impedance transmission lines, 75 ohms differentialy terminated (Fig. 3) :
Each output voltage varies between –1V and –1.42V , leading to +/– 0.41V =0.825 Volt in differential, around –1.21 V
common mode.
2 ) 50 ohms impedance transmission lines, 50 ohms differentialy termination (Fig. 4) :
Each output voltage varies between –1.02V and –1.35V , leading to +/– 0.33V=660 mV in differential, around –1.18V
common mode.
3 ) 75 ohms impedance open transmission lines (Fig. 5) :
Each output voltage varies between –1.6 V and –0.8 V , which are true ECL levels.
Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms trans-
mission lines.
In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to
the generator ( i.e. the 75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflection will
occur.
Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output
impedance.
Each differential output termination length must be kept identical .
It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode
perturbation in case of slight mismatch in the differential output line lengths.
Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the
decoupling capacitor leading to switching ground noise.
The differential output voltage levels ( 75 or 50 ohms termination ) are not ECL standard voltage levels, however it is
possible to drive standard logic ECL circuitry like the ECLinPS logic line from MOTOROLA.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388B | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS |
| TS8388BCF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A/D CONVERTER |
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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