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參數資料
| 型號： | TSB12C01AWN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數： | 54/59頁 |
| 文件大小： | 275K |
| 代理商： | TSB12C01AWN |
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7–6
7.6.3
When data is received by the phy interface from the serial bus, it transfers the data to the TSB12C01A for
further processing. The phy interface asserts receive on the CTL lines and is set to 1 on each D terminal.
The phy interface indicates the start of the packet by placing the speed code on the data bus (see the
following note). The phy interface then proceeds with the transmittal of the packet to the TSB12C01A on
the D lines while still keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the phy interface asserts idle on the CTL terminals that completes the receive operation.
Receive
NOTE:
The speed code sent is a phy-TSB12C01A protocol and not included in the packets
CRC calculation.
SPD = Speed code
D0 => Dn = Packet data
Table 7–10. Speed Code for Receive
D0
–
D7
00xxxxxx
0100xxxx
DATA RATE
100 Mb/s
200 Mb/s
01010000
400 Mb/s
111111111
Data-on indication
The x means transmitted as 0 and ignored by
phy layer.
7.7
TSB12C01A to Phy Bus Timing
LREQ2
LREQ3
LREQ1
LREQ0
LREQn
LREQ
n–1
Figure 7–2. LREQ Timing
Phy
CTL0 – CTL1
01
00
00
00
01
01
01
Phy
D0 – D7
S(14,15)
00
00
00
S(0,1)
S(2,3)
S(4,5)
NOTE A: Each cell represents one SCLK sample time.
Figure 7–3. Status-Transfer Timing
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