- 您現在的位置：買賣IC網 > PDF目錄365968 > TSB14C01HV (Texas Instruments, Inc.) 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER PDF資料下載
參數資料
| 型號： | TSB14C01HV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的電機及電子學工程師聯合會1394-1995背板收發器/仲裁者 |
| 文件頁數： | 28/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14C01HV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
6
–
8
6.2.4
Backplane Transmit Data Timing
Edge separation is the minimum required time between any two consecutive transitions of the backplane bus signals,
as they appear from the output of the transmitters, whether they are transitions on the same signal or transitions on
the two separate signals. A minimum edge separation is required to ensure proper operation of the data strobe
bit-level encoding mechanism. TDATA and TSTRB have the relationship shown in Figure 6
–
7 and Table 6
–
10.
t(2)
t(2)
t(1)
TDATA
TSTRB
t(2)
t(2)
t(1)
t(1)
t(1)
Figure 6
–
7. Minimum Edge Separation
Table 6
–
10. TSB14AA1A to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t(1)
t(2)
This parameter is based on a maximum total transmit skew of 2 ns.
Bit cell period for data
9.44 ns minimum
19.44 ns minimum
Transmit (Tx) edge separation
8.65 ns minimum
18.65 ns minimum
6.2.5
Backplane Receive Data Timing
The receiver typically uses the transitions on the incoming bus signals RDATA and RSTRB to derive a clock at the
code bit frequency to extract the NRZ signal on RDATA. This clock can be derived by performing an exclusive-OR
(XOR) of RDATA and RSTRB.
The bus signals, as they appear from the backplane transceiver media and into the receiver, should fall within the
timing constraints outlined by Figure 6
–
8.
RDATA
RSTRB
t(3)
t(1)
t(1)
t(1)
t(1)
t(2)
t(3)
t(2)
Figure 6
–
8. Backplane Receive Data Timing
Table 6
–
11. TSB14AA1A to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t(1)
t(2)
t(3)
This parameter is based on a maximum total transmit skew of 2 ns and a maximum backplane skew of 0.5 ns.
This assumes total receive skew is less than receive edge separation (i.e., some skew margin exists).
Bit cell period
10.1715 ns nominal
20.34 nominal
Receive (Rx) edge separation
3.4 ns minimum
16.3 ns maximum
3.4 ns minimum
36.6 ns maximum
相關PDF資料 |
PDF描述 |
|---|---|
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB2203X6MMX30M | IC APEX 20KE FPGA 200K 240-PQFP |
| TSB2204.5X12MMX20M | IC APEX 20KE FPGA 200K 240-PQFP |
| TSB2204.5X19MMX20M | IC APEX 20KE FPGA 200K 240-PQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14C01MHV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
| TSB14C01PM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| TSB150002DS | 制造商:TE Connectivity 功能描述: |
| TSB150004DS | 制造商:TE Connectivity 功能描述:Conn Europa Terminal Blocks 8 POS 13.5mm Screw ST Cable Mount 40A/Contact |
發布緊急采購，3分鐘左右您將得到回復。