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參數資料
| 型號： | TSB14C01HV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的電機及電子學工程師聯合會1394-1995背板收發器/仲裁者 |
| 文件頁數： | 6/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14C01HV |
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1
–
1
1 Introduction
1.1
Description
The TSB14AA1A (TSB14AA1A refers to all three devices: TSB14AA1A, TSB14AA1AI, and TSB14AA1AT) is the
second-generation 1394 backplane physical layer device. It is recommended for use in all new designs instead of
the first generation TSB14C01A. It provides the physical layer functions needed to implement a single port node in
a backplane based 1394 network. The TSB14AA1A provides two pins for transmitting, two for receiving, and two pins
to externally control the transceivers for data and strobe. In addition to supporting open-collector drivers, the
TSB14AA1A can also support 3-state
(high-impedance) drivers. The TSB14AA1A is not designed to drive the
backplane directly; this function must be provided externally. The TSB14AA1A is designed to interface with a
link-layer controller (LLC), such as the TSB12LV01B, TSB12LV32, TSB12LV21B, etc.
The TSB14AA1A requires an external 98.304-MHz reference oscillator input for S100 asynchronous only operation
or 49.152-MHz for S50 asynchronous only operation. Two clock select pins (CLK_SEL0, CLK_SEL1) select the
speed mode for the TSB14AA1A (see Table 1
–
1). For S100 operation, the 98.304-MHz reference signal is internally
divided to provide the 49.152-MHz system clock signals used to control transmission of the outbound encoded strobe
and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the
two chips and is used for resynchronization of the received data. For S50 operation, a 49.152-MHz reference signal
is used. This reference signal is internally divided to provide the 24.576-MHz system clock signals for S50 operations.
Table 1
–
1. Speed Mode Setting
SPEED MODE
CLK_SEL0 PIN
CLK_SEL1 PIN
INPUT TO XI PIN
PHY_SCLK OUTPUT
MAXIMUM FREQUENCY
OF TDATA, TSTRB
50 MHz
100 Mbits/s
0
0
100 MHz
X1/2 (50 MHz)
50 Mbits/s
1
0
50 MHz
X1/2 (25 MHz)
25 MHz
Reserved
1
1
—
Reserved
0
1
—
—
—
During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched
internally in the TSB14AA1A in synchronization with the system clock. These bits are combined serially, encoded,
and transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is
transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB.
During packet reception, the data information is received on RDATA and strobe information is received on RSTRB.
The received data and strobe information is decoded to recover the received clock signal and the serial data bits,
which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent
to the associated LLC. The PHY-Link interface has been made compliant to IEEE 1394a
–
2000 including timing and
transfer of register 0 to the link-layer automatically after every 1394 bus reset.
The TSB14AA1A is a 3.3 V device that provides LVCMOS level outputs. The TSB14AA1A is an asynchronous only
device.
3-State means a driver may drive high, low, or may be placed in a high-impedance state
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