欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào)： TSB41LV03AI
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述： IEEE 1394a連接三端口電纜收發(fā)器/仲裁者
文件頁(yè)數(shù)： 35/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41LV03AI
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
LLC service request (continued)
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the
PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then
any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests
if the receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one
clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or
transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears
an isochronous request only when the serial bus has been won.
To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception
of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received
packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY
immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the
header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but
instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant
to send another type of packet. After the interface is released the LLC may proceed with another request.
The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq,
IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request
was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted
control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are
cleared upon a bus reset.
For write register requests, the PHY loads the specified data into the addressed register as soon as the request
transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the
LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the
PHY continues to attempt the transfer of the requested register until it is successful. A write or read register
request may be made at any time, including while a bus request is pending. Once a read register request is
made, the PHY ignores further read register requests until the register contents are successfully transferred to
the LLC. A bus reset does not clear a pending read register request.
The TSB41AB3 includes several arbitration acceleration enhancements, which allow the PHY to improve bus
performance and throughput by reducing the number and length of inter-packet gaps. These enhancements
include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet
concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following
acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.
The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit
the cycle start message under certain circumstances. The acceleration control request is therefore provided
to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41AB3
during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter
rolls over indicating that a cycle start message is imminent, and then reenables the enhancements when it
receives a cycle start message. The acceleration control request may be made at any time, however, and is
immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the
enhancements to be reenabled, if the EAA bit is set.
相關(guān)PDF資料
PDF描述
TSC692E 672-pin FineLine BGA
TSC695F IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC
TSC695FL IC,FPGA,79040-CELL,CMOS,BGA,1020PIN,PLASTIC
TSL1301 102 x 1 Linear Sensor Array with Hold
TSL1401 128 x 1 Linear Sensor Array with Hold
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41LV03AIPFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TSB41LV03APFP 功能描述:緩沖器和線路驅(qū)動(dòng)器 THREE-PORT CABLE XCVR/ARBITER RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
TSB41LV03APFPG4 功能描述:1394 接口集成電路 THREE-PORT CABLE XCVR/ARBITER RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41LV03PFP 制造商:Texas Instruments 功能描述:
TSB41LV03PFP WAF 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*
主站蜘蛛池模板： 平凉市| 固原市| 荣昌县| 专栏| 景德镇市| 仁怀市| 张掖市| 合阳县| 江达县| 年辖：市辖区| 贡嘎县| 邹城市| 辽阳市| 马关县| 瑞昌市| 日土县| 乌拉特前旗| 柳河县| 仁布县| 正蓝旗| 仁化县| 台北市| 枣阳市| 津南区| 仪征市| 彭山县| 镇原县| 南涧| 双鸭山市| 盐山县| 新巴尔虎左旗| 土默特左旗| 饶河县| 淮阳县| 普宁市| 六盘水市| 岑巩县| 东莞市| 松原市| 乡宁县| 元谋县|