- 您現在的位置：買賣IC網 > PDF目錄365968 > TSB43LV81 IC CYCLONE III FPGA 10K 144 EQFP PDF資料下載
參數資料
| 型號： | TSB43LV81 |
| 英文描述： | IC CYCLONE III FPGA 10K 144 EQFP |
| 中文描述： | 總線控制器 |
| 文件頁數： | 8/159頁 |
| 文件大小： | 1085K |
| 代理商： | TSB43LV81 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Page 8
2.1.1.
Physical Interface
The Physical (PHY) interface provides Phy-level service to the LINK layer service. In normal usage, this interface is
connected to internal PHY, but this interface module also allows connecting external PHY. This is useful when multiple
port PHY or Isolation is required.
2.1.2.
LINK_Core (1394.a)
The LINK_Core provide LINK layer service such as transmit and receive correctly formatted IEEE1394-1995 and
IEEE1394.a Asynchronous packets. Also generate and inspect the 32-bits cyclic redundancy check (CRC).
This LINK Core doesn’t have capable Isochronous Service.
2.1.3.
ConfigROM
The ConfigROM module support Auto Response service for Config ROM read request. And also record transaction
history. This module has 528byte of random access memory. ConfigROM provide Configuration ROM that required for
IEEE-1212 standard and Host controller can load its data during node initialization. Before all ConfigROM data is
loaded, LINK_Core return Ack_Tardy to all read requests for this address. Once initialized, ConfigROM is accessible by
peer Node read request.
Log module provides transaction history and has loop FIFO architecture.
Hostcontroller can read most recent transaction packet history that transmitted and received by this node.
(Note) Log Mode is disabled when ConfigRom or Status accesses.
Hostcontroller can set each memory size for above two modules. Refer to CFR 0x8C, 0xF8 and 0xFC for more
information.
2.1.4.
AutoResp
The AutoResp module provide auto packet response service for in-coming request packet.
This AutoResp work for ConfigROM read request, Agent State read request, and error response packet for Un-expected
packet. Some sort of auto error response packet could be disable by control bit for various protocols.
2.1.5.
MICRO I/F
The MICRO I/F module provides Hostcontroller interface. This module could be accessed by 8/16-bit access both of data
address multiplex, 8 bit address data parallel access, and also 16 bit data/8 bit address parallel access when using BDOx
line as address line. This interface has Indian programmable access, and allows most MicroController can access CFR
easily. Refer to section 3 for more information.
2.1.6.
CFR
The CFR(Configuration Resistor) provide most of control bits and also hostcontroller monitor for this node.
Refer to section 3 for more information.
2.1.7.
FOX
The FOX module provide Faster ORB exchanger (FOX) function and support Management ORB and also Command
block ORB transaction. In SBP-2 protocol, target has to read ORB packet from initiators.
This FOX module automatically read both of Management ORB and Command block ORB from initiator when Initiator
requested. Once Management Agent address (CFR 0x48) and other information is set, Hostcontroller does not
have to access each packet until getting ORB packet. Linked Command block ORB is automatically fetched each by each
and hardware can emulate up to 4 Agents.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB43AA22PDT | IC ARRIA GX FPGA 50K 484FBGA |
| TSB43AA82A | IC ARRIA GX FPGA 50K 780FBGA |
| TSB43AB21A | IC ARRIA GX FPGA 60K 484FBGA |
| TSB43AB21A-EP | IC ARRIA GX FPGA 60K 1152FBGA |
| TSB43AA82I | 1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB4559D10-2 | 制造商:Thomas & Betts 功能描述:TRANS CONN 4 POS 500-10 COMPACT DES |
| TSB4559J10C | 制造商:Thomas & Betts 功能描述:4 POS TRANS STUD CONN 500 W/COV |
| TSB5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| TSB5000131DS | 制造商:TE Connectivity 功能描述: |
| TSB5000231 | 制造商:TE Connectivity 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。