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參數資料
| 型號： | TSB43LV81 |
| 英文描述： | IC CYCLONE III FPGA 10K 144 EQFP |
| 中文描述： | 總線控制器 |
| 文件頁數： | 9/159頁 |
| 文件大小： | 1085K |
| 代理商： | TSB43LV81 |
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Page 9
This module have 2 FIFO modules for Management ORB and Command block ORB for both of transmit and receive
packet. Refer to CFR from 0x44 to 0x6C for more detail.
2.1.8.
Packet Distributor
The Packet Distributor module provides packet routing service for each FIFO module.
When SBP-2 mode, all of request packet and response packet have property and rutting to correct FIFO, and also sent to
corresponding initiators. W hen DPP mode, Packet Distributor filtering request packet by its addressing and save it into
correct receive FIFO. Refer to CFR definition for more detail.
2.1.9.
TRMgr
The TRMgr(Transaction Manager) module provide transaction control service which control packet transmit Priority
between control packet and Data packet. Management is simple first in first type control, so, any packet Transmit request
for cable is sent by its order. This module also control split transaction management and busy retry control. If
acknowledge packet for the sent packet is any busy code, module retry to send packet until the packet succeed to transmit
or busy time out. And also, if acknowledge packet for the sent packet is ack_pending, then module start split transaction
timer and waits response packet. If node did not receive Response packet until split transaction time out limit, then the
module set error code and set interrupt.
See CFR specification for more detail.
2.1.10.
Packetizer
The Packetizer module provide packetization for transmit packet. The data stream from BDIF and Bdffifi is split into
small packet that meet SBP-2 requirement. Read request or write request header is attached for each packet and each
header has correctly incremented destination address. These transaction also do busy retry and split transaction timer
control if required. Refer to section for more detail.
The packetizer also provide, AutoPage Table Fetch service, Internal Auto Fetch module send Read Request to page
present address each by each, and DMA automatically send Data to requested address that set by Page Table Element. At
the end of Packetizer, if entire DMA function is completed successfully, then Status Block Packet is automatically sent by
DMA.
2.1.11.
Bdffifo
The Bdffifo module provide data packet FIFO for SBP-2 read response packet and also write request packet. FIFO size is
4736 byte max including received header space, and FIFO size for each Tx and Rx is programmable that set by
Hostcontroller via CFR. Refer to CFR definition for more detail.
2.1.12.
BDif
The BDif module provides data interface between external host DMA and internal FIFO (Bdfifo).
Data is also could be read by Micro I/F in some condition if required. This interface has several mode such as 8/16 bit
width also asynch/synchronous mode. Refer to Bulky interface section for more detail.
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