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參數(shù)資料
| 型號： | TSC2301IPAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 26/95頁 |
| 文件大小： | 1322K |
| 代理商： | TSC2301IPAGRG4 |
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Reference Register (Page 1, Address 03H)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSB
LSB
DPD
X
Bit 15 — DPD
DAC Power Down. This bit controls whether the DAC is powered up and operational, or powered down. If the
DAC is powered down, the AOUT pin neither sinks nor sources current.
Table 12. DPD Bit Operation
DPD
Value
Description
0
DAC is powered and operational
1
DAC is powered down. (default)
This register controls whether the TSC2301 uses an internal or external reference, and if the internal reference is
used, the value of the reference voltage, whether it powers down between conversions and the programmable
settling time after reference power-up. This register is formatted as follows:
Bit 15
Bit 14
Bit 13
Bit 12
Bit
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 LSB
MSB
11
X
INT
DL1
DL0
PDN
RFV
Bit 4 —INT
Internal Reference Mode. If this bit is written to a 1, the TSC2301 uses its internal reference; if this bit is a 0, the
part assumes an external reference is being supplied. The default state for this bit is to select an external
reference (0). This bit is the same whether reading or writing.
Table 13. INT Bit Operation
INT
Value
Description
0
External reference selected (default)
1
Internal reference selected
Bits [3:2] — DL1, DL0
Reference Power-Up Delay. When the internal reference is powered up, a finite amount of time is required for
the reference to settle. If measurements are made before the reference has settled, these measurements are in
error. These bits allow for a delay time for measurements to be made after the reference powers up, thereby
assuring that the reference has settled. Longer delays are necessary depending upon the capacitance present at
the VREFIN pin (see Typical Curves). The delays are shown in Table 14. The default state for these bits is 00,
selecting a 0 microsecond delay. These bits are the same whether reading or writing.
Table 14. Reference Power-Up Delay Settings.
DL1
DL0
DELAY TIME
0
0us (default)
0
1
100 s
1
0
500 s
1
1000 s
Bit 1 —PDN
Reference Power Down. If a 1 is written to this bit, the internal reference are powered down between
conversions. If this bit is a zero, the internal reference is powered at all times. The default state is to power down
the internal reference, so this bit will be a 1. This bit is the same whether reading or writing.
32
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