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參數資料
| 型號： | TSC2301IPAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數： | 77/95頁 |
| 文件大小： | 1322K |
| 代理商： | TSC2301IPAGRG4 |
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
ANALOG AUDIO BYPASS PATH VOLUME CONTROL REGISTER (Page 02, Address 03h)
The bypass path volume control register controls the independent programmable gain amplifiers (PGA's) on the
left and right channel analog audio bypass paths of the TSC2301. These bypass paths direct the line inputs
directly to the line and headphone outputs entirely in the analog domain, with no A/D or D/A conversion. This
feature can be used for playback of an external analog source, such as an FM stereo tuner through the
TSC2301's headphone amplifier. The gain of these PGA's can be adjusted from -35.5 dB to 12 dB in 0.5 dB
steps. The bypass paths can also be muted, so that no signal is transmitted.
The bypass path volume control register is formatted as follows:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSB
LSB
BPMU
BPVL
BPVL5
BPVL4
BPVL3
BPVL
BPMU
BPVR6 BPVR5 BPVR4 BPVR3 BPVR2 BPVR BPVR
L
6
2
1
0
R
1
0
Bit 15 — BPMUL
Left Channel Audio Bypass Mute. This bit is used to mute the bypass path from the left channel line input
(LLINEIN) to the left channel line and headphone outputs (VOUTL and HPL). The user can set this bit to mute
the bypass path while retaining the previous gain setting in BPVL[6:0], so that the PGA returns to the previous
gain setting when BPMUL is cleared. When the BPMUL bit is set, the PGA soft-steps down to its lowest level,
then the bypass path is muted. This procedure is used to reduce any audible artifacts (pops or clicks) during the
mute operation. This soft-stepping process is reversed when the BPMUL bit is cleared (unmute).
Table 42. Left Channel Audio Bypass Mute
BPMUL
Description
0
Left channel audio bypass path is active.
1
Left channel audio bypass path is mute. (default)
Bits [14:8] — BPVL6- BPVL0
Left Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the left channel bypass
path volume control PGA. This volume control can be programmed from -35.5 dB to 12 dB in 0.5 dB steps. Full
volume (+12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation (-35.5
dB) corresponds to 20h. Any value lower than 20h engages the mute function described above. The default
volume setting is 0 dB.
BPVL[6:0] = 1100111 (103d) = 0 dB (default)
BPVL[6:0] = 1111111 (127d) = 12 dB (Max)
BPVL[6:0] = 0100000 (032d) = -35.5 dB (Min)
BPVL[6:0] = 0d-31d = mute
Bit 7 — BPMUR
Right Channel Audio Bypass Mute. This bit is used to mute the bypass path from the right channel line input
(RLINEIN) to the right channel line and headphone outputs (VOUTR and HPR). The user can set this bit to mute
the bypass path while retaining the previous gain setting in BPVR[6:0], so that the PGA returns to the previous
gain setting when BPMUR is cleared. When the BPMUR bit is set, the PGA soft-steps down to its lowest level,
then the bypass path is muted. This procedure is used to reduce any audible artifacts (pops or clicks) during the
mute operation. This soft-stepping process is reversed when the BPMUR bit is cleared (unmute).
Table 43. Right Channel Audio Bypass Mute
BPMUR
Description
0
Right channel audio bypass path is active.
1
Right channel audio bypass path is mute. (default)
79
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| TSC2301IZQZR | 功能描述:觸摸屏轉換器和控制器 Prog 4-Wire w/20-Bit Stereo Audio Codec RoHS:否 制造商:Microchip Technology 類型:Resistive Touch Controllers 輸入類型:3 Key 數據速率:140 SPS 分辨率:10 bit 接口類型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 電源電壓:2.5 V to 5.25 V 電源電流:17 mA 工作溫度:- 40 C to + 85 C 封裝 / 箱體:SSOP-20 |
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