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參數資料
| 型號： | TSPC106AMGS83CE |
| 英文描述： | MEMORY CONTROLLER |
| 中文描述： | 內存控制器 |
| 文件頁數： | 35/40頁 |
| 文件大?。?/td> | 569K |
| 代理商： | TSPC106AMGS83CE |
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35
TSPC106
2102B
–
HIREL
–
02/02
Decoupling
Recommendations
Due to the TSPC106's large address and data buses, and high operating frequencies,
the TSPC106 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be pre-
vented from reaching other components in the system, and the TSPC106 itself requires
a clean, tightly regulated source of power.
It is strongly recommended that the system design include six to eight 0.1 μF (ceramic)
and 10 μF (tantalum) decoupling capacitors to provide both high- and low-frequency fil-
tering. These capacitors should be placed closely around the perimeter of the TSPC106
package (or on the underside of the PCB). It is also recommended that these decou-
pling capacitors receive their power from separate V
DD
and GND power planes in the
PCB, utilizing short traces to minimize inductance. Only SMT (surface mount technol-
ogy) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the V
DD
plane, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance)
rating to ensure the quick response time necessary. They should also be connected to
the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100 μF (AVX TPS tantalum) or 330 μF (AVX TPS tantalum).
Connection
Recommendations
To ensure reliable operation, it is recommended to connect unused inputs to an appro-
priate signal level. Unused active low inputs should be tied (using pull-up resistors) to
V
DD
. Unused active high inputs should be tied (using pull-down resistors) to GND. All
NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, AV
DD
and GND pins
of the TSPC106.
Pull-up Resistor
Recommendations
The TSPC106 requires pull-up (or pull-down) resistors on several control signals of the
60x and PCI buses to maintain the control signals in the negated state after they have
been actively negated and released by the TSPC106 or other bus masters. The JTAG
test reset signal, TRST, should be pulled down during normal system operation. Also, as
indicated in Table 21, the factory test signal, LSSD_MODE, must be pulled up for nor-
mal device operation.
During inactive periods on the bus, the address and transfer attributes on the bus
(A[0:31], TT[0:4], TBST, WT, CI and GBL) are not driven by any master and may float in
the high-impedance state for relatively long periods of time. Since the TSPC106 must
continually monitor these signals, this float condition may cause excessive power draw
by the input receivers on the TSPC106 or by other receivers in the system. It is recom-
mended that these signals be pulled up or restored in some manner by the system.
The 60x data bus input receivers on the TSPC106 do not require pull-up resistors on the
data bus signals (DH[0:31], DL[0:31] and PAR[0:7]). However, other data bus receivers
in the system may require pull-up resistors on these signals.
In general, the 60x address and control signals are pulled up to 3.3 Vdc and the PCI
control signals are pulled up to 5 Vdc through weak (2 - 10 k
) resistors. Resistor val-
ues may need to be adjusted stronger to reduce induced noise on specific board
designs. Table 21 summarizes the pull-up/pull-down recommendations for the
TSPC106.
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相關代理商/技術參數 |
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| TSPC106AMGSB/Q83CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGSB/Q83CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
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