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參數資料
| 型號： | U6220B |
| 英文描述： | 1.3 GHz PLL for TV- and VCR- Tuner |
| 中文描述： | 1.3千兆赫PLL的電視和錄像機，調諧器 |
| 文件頁數： | 6/14頁 |
| 文件大小： | 188K |
| 代理商： | U6220B |
U6220B
TELEFUNKEN Semiconductors
Rev. A2, 23-Sep-96
Preliminary Information
6 (14)
Functional Description
The U6220B is programmed via a 2-wire I
2
C bus or
3-wire bus depending on the received data format. The
three bus inputs Pins 3, 4 and 5 are used as address select,
SDA and SCL inputs in I
2
C bus mode and as ENABLE,
DATA and CLOCK inputs in 3-wire bus mode. The data
includes the scaling factor SF (15/14bit) and switching
output information. In I
2
C bus mode, there are some
additional functions included for testing of the device.
Oscillator frequency calculation:
f
VCO
= 8 x SPF x f
refOSC
/ SRF
f
VCO
:
Locked frequency of voltage controlled
oscillator
SPF:
Scaling factor of programmable divider
(15bit in I
2
C- or 14bit in 3-wire bus mode)
SRF:
Scaling factor of reference divider (
512/
1024/ in I
2
C bus mode or
3-wire bus mode)
f
refOSC
:
Reference oscillator frequency: 3.2/ 4 MHz
crystal or external reference frequency
256/
512 in
This input amplifier together with a divide-by-8 prescaler
provides
excellent
sensitivity
PRESCALER INPUT SENSITIVITY’. The input
impedance is shown in the diagram ‘TYPICAL
IMPEDANCE’. When a new divider ratio according to
(see
‘TYPICAL
the requested f
VCO
is entered, the phase detector and
charge pump together with the tuning amplifier adjusts
the control voltage of the VCO until the output signals of
the programmable divider and the reference divider are in
frequency locked and phase locked. The reference
frequency may be provided by an external source
capacitively coupled into Pin 2, or by using an on-board
crystal with an 18 pF capacitor in series. The crystal
operates in the series resonance mode. In I
2
C bus mode
the reference divider division ratio is selectable to
512/
1024 to two bits of the control byte 2. In 3-wire
bus mode it is fixed to
512. Therefore, with a 4 MHz
crystal and the nominal division ratio of
reference divider, the comparison frequency is
7.8125 kHz, which gives 62.5 kHz steps for the VCO, or
with a 3.2 kHz crystal respectively 6.25 kHz comparison
frequency and 50 kHz VCO step size. In addition, there
are switching outputs available for band switching and
other purposes.
Application
256/
512 of the
A typical application is shown on page 13. All input/
output interface circuits are shown on page 11.
Some special features which are related to test- and
alignment procedures for tuner production are explained
together within the following bus mode description.
I
2
C Bus Description
When the U6220B is controlled via a 2-wire I
2
C bus
format, then data and clock signals are fed into the SDA
and SCL lines respectively. The table ‘I
2
C BUS DATA
FORMAT’ describes the format of the data and shows
how to select the device address by applying a voltage at
Pin 3. When the correct address byte has been received.,
the SDA line is pulled low by the device during the
acknowledge period, and then also during the
acknowledge periods, when additional data bytes are
programmed. After the address transmission (first byte),
data bytes can be sent to the device. There are four data
bytes requested to fully program the device. The table
‘I
2
C BUS PULSE DIAGRAM’ shows some possible data
transfer examples.
Programmable divider bytes PDB1 and PDB2 are stored
in a 15 bit latch and control the division ratio of the 15 bit
programmable divider. The control byte CB1 enables the
control of the following special functions:
–
5l-bit switches between low and high charge pump
current
–
T1-bit enables divider test mode when it is set to
logic 1
–
T0-bit allows to disable the charge pump when it is set
to logic 1
–
RD1-bit and RD2-bit allow to select the reference
divider factor.
–
Os-bit disables the charge pump drive amplifier
output when it is set to logic 1.
The charge pump current can only be controlled in I
2
C
bus mode. In 3-wire bus mode, there is always the high
charge pump current active. The OS-bit function disables
the complete PLL function. This enables the tuner align-
ment by supplying the tuning voltage directly through the
33 V supply voltage of the tuner. The control byte CB2
programs the switching outputs VHF, VHF L/H, UHF, P6,
FM Trap according the band switching logic table on
page 8.
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