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參數資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 200K |
| 代理商： | W127 |
PRELIMINARY
Spread Spectrum 3 DIMM System Frequency Synthesizer w/AGP
W127/W127-A
Cypress Semiconductor Corporation
Document #: 38-07225 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
I
2
C interface
Four copies of CPU Output
Six copies of PCI Output
Two copies of AGP Output
One copy of 48-MHz USB Output
One copy of 24-MHz SIO Output
Twelve copies of SDRAM Output
One buffered copy of 14.318-MHz reference input
Mode input pin selects optional power management in-
put control pins (reconfigures pins 29, 30, 31, and 32)
Smooth frequency transition upon frequency
reselection
Available in 48-pin SSOP (300 mils)
Standard W127 device supports up to 112-MHz opera-
tions. High-performance option W127-A supports up to
124-MHz.
Key Specifications
Supply Voltages:.......... V
DDQ3
= 3.3V, V
DDQ2
= 3.3V or 2.5V
CPU Cycle to Cycle Jitter:...........................................250 ps
CPU to AGP Skew: .................................................
0±500 ps
AGP to PCI Skew:..................................1.5 ns (AGP Leads)
CPU Output Edge Rate:............................................ >1 V/ns
SDRAM Output Edge Rate:.................................... >1.5 V/ns
Note:
All skews are optimized @V
DDQ2
= V
DDQ3
= 3.3V±5%.
Skews are not guaranteed for V
DDQ2
= 2.5V.
Table 1. Pin Selectable Frequency
[1]
Input Address
CPU
(MHz)
FS2
FS1
FS0
0
0
0
68.5
0
0
1
112
0
1
0
95.25
0
1
1
100
1
0
0
83.3
1
0
1
75.0
1
1
0
124
1
1
1
66.6
.
Notes:
1.
2.
Configuration
“
110
”
is supported by W127-A only (see shaded row of
Table 1
).
Signal names with
“
*
”
denote pins have internal 250K pull-up resistor, though not relied upon for pulling to V
DDQ3
. Signal names with parenthesis denote function
is selectable by MODE pin strapping.
AGP
(MHz)
68.5
74.6
63.5
66.6
55.53
75
82.6
66.6
PCI
(MHz)
34.25
37.3
31.75
33.3
27.77
37.5
41.3
33.3
Block Diagram
Pin Configuration
[2]
VDDQ3
VDDQ3
REF/SD_SEL*
GND
X1
X2
VDDQ3
PCI_F/FS2*
PCI0
GND
PCI1
PCI2
PCI3
PCI4
GND
GND
AGP_F/MODE*
AGP0
VDDQ3
SDRAM11
SDRAM10
VDDQ3
SDATA
VDDQ3
W
48MHz/FS1*
24MHz/FS0*
GND
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4(AGP_STOP#)*
SDRAM5(PWR_DWN#)*
SDRAM6(CPU_STOP#)*
SDRAM7(PCI_STOP#)*
GND
SDRAM8
SDRAM9
SCLOCK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ3
SDRAM0:11
AGP_F/MODE
AGP0
XTAL OSC
PLL Ref
Freq
÷
1
X2
X1
PCI_F/FS2
(PWR_DWN#)
Power Down
Control
48MHZ/FS1
24MHZ/FS0
PLL2
Serial Port
SCLOCK
SDATA
Device
Control
(CPU_STOP#)
÷
2
÷
1
I/O
I/O
VDDQ3
12
÷
2
I/O
REF/SD_SEL
PLL1
÷
1.5
CPU0:3
CPU
STOP
PCI0:4
AGP
STOP
(AGP_STOP#)
PCI
STOP
(PCI_STOP#)
SDRAM
STOP
I/O
I/O
/
5
4
VDDQ3
VDDQ2
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