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參數資料
| 型號： | W256H |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 12 Output Buffer for 2 DDR and 3 SRAM DIMMS |
| 中文描述： | 256 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數： | 3/9頁 |
| 文件大小： | 176K |
| 代理商： | W256H |
W256
Document #: 38-07256 Rev. *C
Page 3 of 9
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 — Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 — Bits 7, 6, 5, 4, 3, 2, 1, 0
.–
.
Byte N — Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to “0”.
SMBus Address for the W256 is:
Table 1.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
––
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin #
–
–
–
1
27, 26
Description
Default
0
0
0
1
1
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
FBOUT
DDR5T_SDRAM10,
DDR5C_SDRAM11
Reserved, drive to 0
DDR4T_SDRAM8,
DDR4C_SDRAM9
Reserved, drive to 0
Bit 2
Bit 1
–
1
1
23, 22
Bit 0
–
1
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Pin #
–
19, 18
Description
Default
1
1
Reserved, drive to 0
DDR3T_SDRAM6,
DDR3C_SDRAM7
DDR2T_SDRAM4,
DDR2C_SDRAM5
Reserved, drive to 0
Reserved, drive to 0
DDR1T_SDRAM2,
DDR1C_SDRAM3
Reserved, drive to 0
DDR0T_SDRAM0,
DDR0C_SDRAM1
Bit 5
12, 13
1
Bit 4
Bit 3
Bit 2
–
–
1
1
1
7, 8
Bit 1
Bit 0
–
1
1
3, 4
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