- 您現在的位置：買賣IC網 > PDF目錄21988 > XC2S150-5PQG208C (Xilinx Inc)IC SPARTAN-II FPGA 150K 208-PQFP PDF資料下載
參數資料
| 型號： | XC2S150-5PQG208C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 10/99頁 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-II FPGA 150K 208-PQFP |
| 標準包裝： | 24 |
| 系列： | Spartan®-II |
| LAB/CLB數： | 864 |
| 邏輯元件/單元數： | 3888 |
| RAM 位總計： | 49152 |
| 輸入/輸出數： | 140 |
| 門數： | 150000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 產品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1308 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
18
R
Signals
There are two kinds of pins that are used to configure
Spartan-II devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an
input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
For a more detailed description than that given below, see
"Pinout Tables" in Module 4 and XAPP176, Spartan-II
FPGA Series Configuration and Readback.
The Process
The sequence of steps necessary to configure Spartan-II
devices are shown in Figure 11. The overall flow can be
divided into three different phases.
Initiating Configuration
Configuration memory clear
Loading data frames
Start-up
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
Initiating Configuration
There are two different ways to initiate the configuration
process: applying power to the device or asserting the
PROGRAM input.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
shown in Figure 12, page 19. Before configuration can
begin, VCCO Bank 2 must be greater than 1.0V.
Furthermore, all VCCINT power pins must be connected to a
2.5V supply. For more information on delaying
configuration, see "Clearing Configuration Memory,"
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process
by driving DONE Low, then enters the memory-clearing
phase.
Figure 11: Configuration Flow Diagram
FPGA Drives
INIT Low
Abort Start-up
User Holding
INIT
Low?
User Holding
PROGRAM
Low?
FPGA
Drives INIT
and DONE Low
Load
Configuration
Data Frames
User Operation
Configuration
at Power-up
DS001_11_111501
No
CRC
Correct?
Yes
FPGA
Samples
Mode Pins
Delay
Configuration
Delay
Configuration
Clear
Configuration
Memory
User Pulls
PROGRAM
Low
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
Yes
No
Yes
No
Yes
Configuration During
User Operation
VCCO
AND
VCCINT
High?
相關PDF資料 |
PDF描述 |
|---|---|
| TACR685K010R | CAP TANT 6.8UF 10V 10% 0805 |
| GMC43DRAS-S734 | CONN EDGECARD 86POS .100 R/A SLD |
| AMC18DRYS-S734 | CONN EDGECARD 36POS DIP .100 SLD |
| FMC10DREN-S13 | CONN EDGECARD 20POS .100 EXTEND |
| XC3S250E-4PQG208C | IC SPARTAN-3E FPGA 250K 208-PQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S150-5PQG208I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 150K GATES 3888 CELLS 263MHZ 2.5V 208PQFP - Trays |
| XC2S150-5TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5TQG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5TQG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
發布緊急采購，3分鐘左右您將得到回復。