- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄21988 > XC2S150-5PQG208C (Xilinx Inc)IC SPARTAN-II FPGA 150K 208-PQFP PDF資料下載
參數(shù)資料
| 型號： | XC2S150-5PQG208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 66/99頁 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-II FPGA 150K 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 864 |
| 邏輯元件/單元數(shù)： | 3888 |
| RAM 位總計： | 49152 |
| 輸入/輸出數(shù)： | 140 |
| 門數(shù)： | 150000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 產(chǎn)品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1308 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當(dāng)前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
DS001-4 (v2.8) June 13, 2008
Module 4 of 4
Product Specification
69
2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
Introduction
This section describes how the various pins on a
Spartan-II FPGA connect within the supported component
packages, and provides device-specific thermal
characteristics. Spartan-II FPGAs are available in both
standard and Pb-free, RoHS versions of each package,
with the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
information for the standard package applies equally to the
Pb-free package.
Pin Types
Most pins on a Spartan-II FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-II FPGA packages, as
outlined in Table 35.
99
Spartan-II FPGA Family:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
Product Specification
R
Table 35: Pin Definitions
Pin Name
Dedicated
Direction
Description
GCK0, GCK1, GCK2,
GCK3
No
Input
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
M0, M1, M2
Yes
Input
Mode pins are used to specify the configuration mode.
CCLK
Yes
Input or Output
The configuration Clock I/O pin. It is an input for slave-parallel and slave-serial
modes, and output in master-serial mode.
PROGRAM
Yes
Input
Initiates a configuration sequence when asserted Low.
DONE
Yes
Bidirectional
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output may be open drain.
INIT
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared. This pin
becomes a user I/O after configuration.
BUSY/DOUT
No
Output
In Slave Parallel mode, BUSY controls the rate at which configuration data is
loaded. This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to downstream devices in
a daisy-chain. This pin becomes a user I/O after configuration.
D0/DIN, D1, D2, D3, D4,
D5, D6, D7
No
Input or Output
In Slave Parallel mode, D0-D7 are configuration data input pins. During
readback, D0-D7 are output pins. These pins become user I/Os after
configuration unless the Slave Parallel port is retained.
In serial modes, DIN is the single data input. This pin becomes a user I/O after
configuration.
WRITE
No
Input
In Slave Parallel mode, the active-low Write Enable signal. This pin becomes
a user I/O after configuration unless the Slave Parallel port is retained.
CS
No
Input
In Slave Parallel mode, the active-low Chip Select signal. This pin becomes a
user I/O after configuration unless the Slave Parallel port is retained.
TDI, TDO, TMS, TCK
Yes
Mixed
Boundary Scan Test Access Port pins (IEEE 1149.1).
VCCINT
Yes
Input
Power supply pins for the internal core logic.
VCCO
Yes
Input
Power supply pins for output drivers (subject to banking rules)
VREF
No
Input
Input threshold voltage pins. Become user I/Os when an external threshold
voltage is not needed (subject to banking rules).
GND
Yes
Input
Ground.
IRDY, TRDY
No
See PCI core
documentation
These signals can only be accessed when using Xilinx PCI cores. If the
cores are not used, these pins are available as user I/Os.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TACR685K010R | CAP TANT 6.8UF 10V 10% 0805 |
| GMC43DRAS-S734 | CONN EDGECARD 86POS .100 R/A SLD |
| AMC18DRYS-S734 | CONN EDGECARD 36POS DIP .100 SLD |
| FMC10DREN-S13 | CONN EDGECARD 20POS .100 EXTEND |
| XC3S250E-4PQG208C | IC SPARTAN-3E FPGA 250K 208-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S150-5PQG208I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 150K GATES 3888 CELLS 263MHZ 2.5V 208PQFP - Trays |
| XC2S150-5TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5TQG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5TQG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。