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參數(shù)資料
| 型號： | 48SD6404RPFK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 中文描述： | 64M X 4 SYNCHRONOUS DRAM, 6 ns, DFP72 |
| 封裝： | DFP-72 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大小： | 596K |
| 代理商： | 48SD6404RPFK |
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48SD6404
M
em
o
ry
20
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
Operation of the SDRAM
The following section shows operation examples of 48SD6404.
Note: The SDRAM should be used according to the product capability ( See Pin Description and AC
Characteristics.)
Read/Write Operations:
Bank Active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. An interval of t
RCD is required between the bank active
command input and the following read/write command input.
Read operation: A read operation starts when a read command is input. The output buffer becomes Low-Z
in the (CAS latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4, or 8. The start address for a burst read is specified by the column
address and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the CAS latency. The CAS latency can be set to 2 or 3.
When the burst length is 1, 2, 4, or 8, the D
OUT buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The CAS latency and burst length must be specified at the mode register.
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