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參數資料
| 型號： | 73S1209F-68IMR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁數： | 108/123頁 |
| 文件大小： | 1385K |
| 代理商： | 73S1209F-68IMR/F |
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DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
85
TX Control/Status Register (STXCtl): 0xFE06
0x00
This register is used to control transmission of data to the smart card. Some control and some status bits
are in this register.
Table 79: The STXCtl Register
MSB
LSB
SYCKST
–
TXFULL TXEMTY TXUNDR LASTTX
TX/RXB BREAKD
Bit
Symbol
Function
STXCtl.7
I2CMODE
I2C Mode – When in sync mode and this bit is set, and when the RLen count
value = max or 0, the source of the smart card data for IO pin (or SIO pin) will
FIFO. See the description for the Protocol Mode Register for more detail.
STXCtl.6
–
STXCtl.5
TXFULL
TX FIFO is full. Additional writes may corrupt the contents of the FIFO. This
bit it will remain set as long as the TX FIFO is full. Generates TX_Event
interrupt upon going full.
STXCtl.4
TXEMTY
1 = TX FIFO is empty, 0 = TX FIFO is not empty. If there is data in the TX
FIFO, the circuit will transmit it to the smart card if in transmit mode. In T=1
mode, if the LASTTX bit is set and the hardware is configured to transmit the
CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. In
T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has
been successfully transmitted to the smart card. Generates TXEVNT
interrupt upon going empty.
STXCtl.3
TXUNDR
TX Underrrun – (Read only) Asserted when a transmit under-run condition
has occurred. An under-run condition is defined as an empty TX FIFO when
the last data word has been successfully transmitted to the smart card and
the LASTTX bit was not set. No special processing is performed by the
hardware if this condition occurs. Cleared when read by firmware. This bit
generates TXERR interrupt.
STXCtl.2
LASTTX
Last TX Byte – Set by firmware (in both T=0 and T=1) when the last byte in
the current message has been written into the transmit FIFO. In T=1 mode,
the CRC/LRC will be appended to the message. Should be set after the last
byte has been written into the transmit FIFO. Should be cleared by firmware
before writing first byte of next message into the transmit FIFO. Used in T=0
to determine when to set TXEMTY.
STXCtl.1
TX/RXB
1 = Transmit mode, 0 = Receive mode. Configures the hardware to be
receiving from or transmitting to the smart card. Determines which counters
should be enabled. This bit should be set to receive mode prior to switching
to another interface. Setting and resetting this bit shall initialize the CRC
logic. If LASTTX is set, this bit can be reset to RX mode and UART logic will
automatically change mode to RX when TX operation is completed
(TX_Empty =1).
STXCtl.0
BREAKD
Break Detected – (Read only) 1 = A break has been detected on the I/O line
indicating that the smart card detected a parity error. Cleared when read.
This bit generates TXERR interrupt.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 73S1209F-68M/F/P1 | 功能描述:8位微控制器 -MCU Contained 80515-SoC Serial Hst Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| 73S1209F-EB | 功能描述:開發板和工具包 - 8051 73S1209F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
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